This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
093e287a1e
yosys
/
tests
/
opt
/
opt_expr_constconn.v
9 lines
96 B
Verilog
Raw
Blame
History
module
top
(
.
.
.
)
;
input
[
7
:
0
]
A
;
output
[
7
:
0
]
B
;
wire
[
7
:
0
]
C
=
3
;
assign
B
=
A
+
C
;
endmodule
Reference in New Issue
View Git Blame
Copy Permalink