yosys/tests/opt/opt_expr_constconn.v

module top(...);

input [7:0] A;
output [7:0] B;
wire [7:0] C = 3;
assign B = A + C;

endmodule
opt_expr: Propagate constants to port connections. This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass. 2021-07-27 08:24:48 -05:00			`module top(...);`

			`input [7:0] A;`
			`output [7:0] B;`
			`wire [7:0] C = 3;`
			`assign B = A + C;`

			`endmodule`