This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
084685f480
yosys
/
passes
History
Clifford Wolf
084685f480
Implemented "rename -enumerate -pattern"
2014-08-26 12:51:08 +02:00
..
abc
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_
2014-08-16 18:29:39 +02:00
cmds
Implemented "rename -enumerate -pattern"
2014-08-26 12:51:08 +02:00
fsm
Added module->uniquify()
2014-08-16 23:50:36 +02:00
hierarchy
Added module->ports
2014-08-14 16:22:52 +02:00
memory
Various improvements in memory_dff pass
2014-08-06 14:31:38 +02:00
opt
Optimize shift ops with constant rhs in opt_const
2014-08-24 17:08:43 +02:00
proc
Fixed handling of constant-true branches in proc_clean
2014-08-12 17:35:22 +02:00
sat
azonenberg: Make dump_vcd save model when temporal induction fails due to step limit
2014-08-24 13:27:40 +02:00
techmap
Only call proc_share_dirname() in techmap when necessary
2014-08-23 15:32:00 +02:00
tests
Changed backend-api from FILE to std::ostream
2014-08-23 13:54:21 +02:00