mirror of https://github.com/YosysHQ/yosys.git
eb5da87d52
Filling out the hardware mapping sections, and actually highlighting the changes in schematics instead of just the memory block. Also includes Part 4 of the coarse-grain rep, looking at `memory_collect` and putting the `synth_ice40 -top fifo -run :map_ram` command in its own (sub)section. Includes a `no_rw_check` section label in `memory.rst` for reference (because I can't remember how to reference by heading). Not sure about the opt output after map_ram section which has an open TODO, and the final steps section is also still open. |
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| Makefile | ||
| fifo.out | ||
| fifo.v | ||
| fifo.ys | ||
| fifo_map.ys | ||