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yosys/backends/verilog
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Catherine 0486f61a35 write_verilog: emit zero width parameters as `.PARAM()`. 2024-01-11 13:13:04 +01:00
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Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: emit zero width parameters as `.PARAM()`. 2024-01-11 13:13:04 +01:00