Charlotte 04582f2fb7 verilog_backend: emit sync `$print` cells with same triggers together ... Sort by PRIORITY, ensuring output order.		2023-08-11 04:46:52 +02:00
..
fuzz	fmt: merge fuzzers since we don't rely on BigInteger logic	2023-08-11 04:46:52 +02:00
.gitignore	fmt: add tests for Verilog round trip of format expressions.	2023-08-11 04:46:52 +02:00
always_comb.v	cxxrtl: WIP: adjust comb display cells to only fire on change	2023-08-11 04:46:52 +02:00
always_comb_tb.cc	cxxrtl: store comb $print cell last EN/ARGS in module	2023-08-11 04:46:52 +02:00
always_comb_tb.v	cxxrtl: store comb $print cell last EN/ARGS in module	2023-08-11 04:46:52 +02:00
always_display.v	fmt: add tests for Verilog round trip of format expressions.	2023-08-11 04:46:52 +02:00
always_full.v	verilog_backend: emit sync `$print` cells with same triggers together	2023-08-11 04:46:52 +02:00
always_full_tb.cc	verilog_backend: emit sync `$print` cells with same triggers together	2023-08-11 04:46:52 +02:00
always_full_tb.v	verilog_backend: emit sync `$print` cells with same triggers together	2023-08-11 04:46:52 +02:00
display_lm.v	fmt: rudimentary %m support (= %l)	2023-08-11 04:46:52 +02:00
display_lm_tb.cc	fmt: rudimentary %m support (= %l)	2023-08-11 04:46:52 +02:00
initial_display.v	fmt: format %t consistently at initial	2023-08-11 04:46:52 +02:00
roundtrip.v	fmt: add tests for Verilog round trip of format expressions.	2023-08-11 04:46:52 +02:00
roundtrip_tb.v	fmt: add tests for Verilog round trip of format expressions.	2023-08-11 04:46:52 +02:00
run-test.sh	verilog_backend: emit sync `$print` cells with same triggers together	2023-08-11 04:46:52 +02:00