yosys/passes
Clifford Wolf 03c96f9ce7 Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00
..
abc Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
cmds Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
fsm Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
hierarchy Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
memory Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
opt Added $shift and $shiftx cell types (needed for correct part select behavior) 2014-07-29 16:35:13 +02:00
proc Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
sat Using log_assert() instead of assert() 2014-07-28 11:27:48 +02:00
techmap Added "techmap -map %{design-name}" 2014-07-29 16:35:13 +02:00