Clifford Wolf ddc1761f1a Add "make coverage" ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2018-08-27 14:22:21 +02:00
..
.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
Makefile.inc	Add "make coverage"	2018-08-27 14:22:21 +02:00
const2ast.cc	Convert more log_error() to log_file_error() where possible.	2018-07-20 09:37:44 -07:00
preproc.cc	Support SystemVerilog `` extension for macros	2018-05-17 00:09:56 -04:00
verilog_frontend.cc	Added -no_dump_ptr flag for AST dump options in 'read_verilog'	2018-08-23 15:26:02 +03:00
verilog_frontend.h	Remember global declarations and defines accross read_verilog calls	2016-11-15 12:42:43 +01:00
verilog_lexer.l	Add "make coverage"	2018-08-27 14:22:21 +02:00
verilog_parser.y	Fixed all known specify/endspecify issues, without breaking 'make test'.	2018-08-20 17:27:45 +03:00