yosys/passes
Eddie Hung fb4348f840 Fix for when B_WIDTH has trailing zeroes 2019-04-25 19:38:19 -07:00
..
cmds Merge branch 'xaig' into xc7mux 2019-04-22 11:58:59 -07:00
equiv Add "techmap -wb", use in formal flows 2019-04-20 11:23:24 +02:00
fsm fsm_opt: Fix runtime error for FSMs without a reset state 2019-02-07 10:35:36 +00:00
hierarchy Add "whitebox" attribute, add "read_verilog -wb" 2019-04-18 17:45:47 +02:00
memory memory_bram: Fix multiport make_transp 2019-04-07 16:56:31 +01:00
opt Remove some left-over log_dump() 2019-04-23 17:55:41 +02:00
pmgen Fix for when B_WIDTH has trailing zeroes 2019-04-25 19:38:19 -07:00
proc Improve proc full_case detection and handling, fixes #931 2019-04-18 15:13:47 +02:00
sat Merge remote-tracking branch 'origin/xc7srl' into xc7mux 2019-04-22 11:45:49 -07:00
techmap Merge pull request #914 from YosysHQ/xc7srl 2019-04-22 13:31:30 -07:00
tests flowmap: implement depth relaxation. 2019-01-08 01:13:05 +00:00