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yosys/frontends/verilog
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Clifford Wolf b5a3419ac2 Added support for non-standard "module mod_name(...);" syntax 2014-08-04 15:40:07 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Added "make PRETTY=1" 2014-07-24 17:15:01 +02:00
const2ast.cc Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
lexer.l Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
parser.y Added support for non-standard "module mod_name(...);" syntax 2014-08-04 15:40:07 +02:00
preproc.cc Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
verilog_frontend.cc Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00
verilog_frontend.h Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace 2014-07-31 13:19:47 +02:00