Clifford Wolf 0129d41efa Fixed AST handling of variables declared inside a functions main block		2014-08-05 08:35:51 +02:00
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ast	Fixed AST handling of variables declared inside a functions main block	2014-08-05 08:35:51 +02:00
ilang	Renamed port access function on RTLIL::Cell, added param access functions	2014-07-31 16:38:54 +02:00
liberty	More bugfixes related to new RTLIL::IdString	2014-08-02 18:14:21 +02:00
verific	Fixed build of verific bindings	2014-07-31 16:45:23 +02:00
verilog	Added support for non-standard "module mod_name(...);" syntax	2014-08-04 15:40:07 +02:00
vhdl2verilog	Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace	2014-07-31 13:19:47 +02:00