mirror of https://github.com/YosysHQ/yosys.git
30 lines
421 B
Plaintext
30 lines
421 B
Plaintext
read_verilog -nomem2reg port_sign_extend.v
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hierarchy
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flatten
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proc
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memory
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equiv_make ref act equiv
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equiv_simple
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equiv_status -assert
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delete
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read_verilog -nomem2reg port_sign_extend.v
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flatten
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proc
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memory
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equiv_make ref act equiv
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equiv_simple
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equiv_status -assert
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delete
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read_verilog -nomem2reg port_sign_extend.v
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hierarchy
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proc
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memory
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equiv_make ref act equiv
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prep -flatten -top equiv
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equiv_induct
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equiv_status -assert
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