riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/various/port_sign_extend.ys

30 lines
421 B
Plaintext
Raw Normal View History

genrtlil: fix signed port connection codegen failures This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
2021-02-05 18:38:10 -06:00
read_verilog -nomem2reg port_sign_extend.v
Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
2020-12-18 13:59:08 -06:00
hierarchy
flatten
genrtlil: fix signed port connection codegen failures This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
2021-02-05 18:38:10 -06:00
proc
memory
Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
2020-12-18 13:59:08 -06:00
equiv_make ref act equiv
equiv_simple
equiv_status -assert
delete
genrtlil: fix signed port connection codegen failures This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
2021-02-05 18:38:10 -06:00
read_verilog -nomem2reg port_sign_extend.v
Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
2020-12-18 13:59:08 -06:00
flatten
genrtlil: fix signed port connection codegen failures This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
2021-02-05 18:38:10 -06:00
proc
memory
Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
2020-12-18 13:59:08 -06:00
equiv_make ref act equiv
equiv_simple
equiv_status -assert
delete
genrtlil: fix signed port connection codegen failures This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
2021-02-05 18:38:10 -06:00
read_verilog -nomem2reg port_sign_extend.v
Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
2020-12-18 13:59:08 -06:00
hierarchy
genrtlil: fix signed port connection codegen failures This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
2021-02-05 18:38:10 -06:00
proc
memory
Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
2020-12-18 13:59:08 -06:00
equiv_make ref act equiv
prep -flatten -top equiv
genrtlil: fix signed port connection codegen failures This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
2021-02-05 18:38:10 -06:00
equiv_induct
Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
2020-12-18 13:59:08 -06:00
equiv_status -assert