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yosys/tests/various/port_sign_extend.ys

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Sign extend port connections where necessary - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
2020-12-18 13:59:08 -06:00
read_verilog port_sign_extend.v
hierarchy
flatten
equiv_make ref act equiv
equiv_simple
equiv_status -assert
delete
read_verilog port_sign_extend.v
flatten
equiv_make ref act equiv
equiv_simple
equiv_status -assert
delete
read_verilog port_sign_extend.v
hierarchy
equiv_make ref act equiv
prep -flatten -top equiv
equiv_status -assert