yosys/tests/techmap/bug2321.ys

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read_verilog <<EOT
module m (input i, output o);
wire [1023:0] _TECHMAP_DO_00_ = "CONSTMAP; ";
endmodule
EOT
design -stash map
read_verilog <<EOT
module top(output o);
m m (.o(o), .i(o));
endmodule
EOT
techmap -map %map