mirror of https://github.com/YosysHQ/yosys.git
16 lines
223 B
Plaintext
16 lines
223 B
Plaintext
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read_verilog <<EOT
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module m (input i, output o);
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wire [1023:0] _TECHMAP_DO_00_ = "CONSTMAP; ";
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endmodule
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EOT
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design -stash map
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read_verilog <<EOT
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module top(output o);
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m m (.o(o), .i(o));
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endmodule
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EOT
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techmap -map %map
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