mirror of https://github.com/YosysHQ/yosys.git
139 lines
5.1 KiB
Plaintext
139 lines
5.1 KiB
Plaintext
# ================================ RAM ================================
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# RAM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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## With parameters
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # too inefficient
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select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "block_ram" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "Block_RAM" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K # any case works
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set ram_block 1 m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set syn_ramstyle "registers" m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
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select -assert-min 1 t:SB_DFFE
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design -reset; read_verilog -defer ../common/blockram.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_ram_sdp
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hierarchy -top sync_ram_sdp
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setattr -set logic_block 1 m:memory
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synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
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select -assert-count 0 t:SB_RAM40_4K # requested FFRAM explicitly
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select -assert-min 1 t:SB_DFFE
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# ================================ ROM ================================
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# ROM bits <= 4K; Data width <= 16; Address width <= 11: -> SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_rom
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hierarchy -top sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_rom
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hierarchy -top sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 8 sync_rom
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hierarchy -top sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 16 sync_rom
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hierarchy -top sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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## With parameters
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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hierarchy -top sync_rom
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # too inefficient
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select -assert-min 1 t:SB_LUT4
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "ebr" m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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hierarchy -top sync_rom
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setattr -set rom_block 1 m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 1 t:SB_RAM40_4K
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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hierarchy -top sync_rom
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setattr -set syn_romstyle "logic" m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
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select -assert-min 1 t:SB_LUT4
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design -reset; read_verilog -defer ../common/blockrom.v
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chparam -set ADDRESS_WIDTH 2 -set DATA_WIDTH 8 sync_rom
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hierarchy -top sync_rom
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setattr -set logic_block 1 m:memory
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synth_ice40 -top sync_rom; cd sync_rom
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select -assert-count 0 t:SB_RAM40_4K # requested LUTROM explicitly
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select -assert-min 1 t:SB_LUT4
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