..
Makefile.inc
Add missing file for XO3D
2023-09-01 10:15:51 +02:00
arith_map_ccu2c.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
arith_map_ccu2d.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
brams_8kc.txt
lattice: Disable broken port configuration in bram inference
2023-12-21 10:47:40 +01:00
brams_16kd.txt
Create synth_lattice
2023-08-23 10:53:21 +02:00
brams_map_8kc.v
lattice: Fix mapping onto DP8KC for data width 1 or 2
2023-12-20 23:42:12 +01:00
brams_map_16kd.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
ccu2c_sim.vh
Create synth_lattice
2023-08-23 10:53:21 +02:00
ccu2d_sim.vh
Create synth_lattice
2023-08-23 10:53:21 +02:00
cells_bb_ecp5.v
fix generated blackboxes for ecp5
2023-08-28 16:26:26 +02:00
cells_bb_xo2.v
enable more primitives supported with nextpnr
2023-08-25 11:45:25 +02:00
cells_bb_xo3.v
enable more primitives supported with nextpnr
2023-08-25 11:45:25 +02:00
cells_bb_xo3d.v
enable more primitives supported with nextpnr
2023-08-25 11:45:25 +02:00
cells_ff.vh
Create synth_lattice
2023-08-23 10:53:21 +02:00
cells_io.vh
Create synth_lattice
2023-08-23 10:53:21 +02:00
cells_map.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
cells_sim_ecp5.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
cells_sim_xo2.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
cells_sim_xo3.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
cells_sim_xo3d.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
cells_xtra.py
fix generated blackboxes for ecp5
2023-08-28 16:26:26 +02:00
common_sim.vh
enable more primitives supported with nextpnr
2023-08-25 11:45:25 +02:00
dsp_map_18x18.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
latches_map.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
lattice_gsr.cc
ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech
2023-08-22 10:50:11 +02:00
lutrams.txt
Create synth_lattice
2023-08-23 10:53:21 +02:00
lutrams_map.v
Create synth_lattice
2023-08-23 10:53:21 +02:00
synth_lattice.cc
Fix some synth_* help messages
2024-03-18 11:33:18 +13:00