Eddie Hung
fb09c6219b
Merge remote-tracking branch 'origin/master' into xc7mux
2019-05-21 14:21:00 -07:00
Clifford Wolf
05a5027db8
Add $stop to documentation
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-09 15:31:40 +02:00
Clifford Wolf
e2fb8ebe86
Update README
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:01:39 +02:00
Eddie Hung
dcc8a13e48
Revert "Merge branch 'eddie/split_shiftx' into xc7mux"
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This reverts commit 3042d58330
, reversing
changes made to feff976454
.
2019-04-26 15:32:02 -07:00
Clifford Wolf
67005633e2
Add specify support to README
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-23 23:01:38 +02:00
Eddie Hung
c6156f3118
Format some names using inline code
2019-04-23 09:01:10 -07:00
Eddie Hung
f66792c43a
Fix spelling
2019-04-23 08:58:34 -07:00
Clifford Wolf
99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings
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Feature/python bindings
2019-04-22 14:47:52 +02:00
Clifford Wolf
5b7fea5245
Add "noblackbox" attribute
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-21 11:40:09 +02:00
Clifford Wolf
fb7f02be55
New behavior for front-end handling of whiteboxes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-20 22:24:50 +02:00
Clifford Wolf
f4abc21d8a
Add "whitebox" attribute, add "read_verilog -wb"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-18 17:45:47 +02:00
whitequark
6323e73cc9
README: fix some incorrect quoting.
2019-04-15 14:29:46 +00:00
Benedikt Tutzer
e64b3f1074
Changed filesystem dependency to boost instead of experimental std library
2019-04-04 09:24:50 +02:00
Benedikt Tutzer
d287596be3
Added dependencies to README and travis configuration
2019-04-03 11:18:34 +02:00
Clifford Wolf
d0b9b1bece
Add "hdlname" attribute
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-26 14:52:48 +01:00
Felix Vietmeyer
a71c38f163
Add note about test requirements in README
2019-03-16 06:20:59 -06:00
Clifford Wolf
ae9286386d
Only run derive on blackbox modules when ports have dynamic size
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-02 12:36:46 -08:00
Clifford Wolf
a02d61576e
Minor improvements in README
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-01 14:29:17 -08:00
whitequark
efa278e232
Fix typographical and grammatical errors and inconsistencies.
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The initial list of hits was generated with the codespell command
below, and each hit was evaluated and fixed manually while taking
context into consideration.
DIRS="kernel/ frontends/ backends/ passes/ techlibs/"
DIRS="${DIRS} libs/ezsat/ libs/subcircuit"
codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint
More hits were found by looking through comments and strings manually.
2019-01-02 13:12:17 +00:00
Clifford Wolf
f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces
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Support for SystemVerilog interfaces and modports
2018-10-18 10:58:47 +02:00
Clifford Wolf
debc0d3515
We have 2018 now
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-10-16 16:51:58 +02:00
Ruben Undheim
c50afc4246
Documentation improvements etc.
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- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
2018-10-13 20:34:44 +02:00
Miodrag Milanovic
c5e9034834
Fix Cygwin build and document needed packages
2018-09-19 10:16:53 +02:00
Konrad Beckmann
da53206cd4
readme: Fix formatting of a keyword
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Single quotes were used instead of backticks leading to
incorrect formatting.
2018-08-06 13:33:02 +09:00
Clifford Wolf
4372cf690d
Add (* gclk *) attribute support
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-06-01 13:25:42 +02:00
Clifford Wolf
4b6c0e331d
Remove mercurial from build instructions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-05-15 14:19:05 +02:00
Johnny Sorocil
5b9f73cd91
update README
2018-05-06 18:22:18 +02:00
Clifford Wolf
035f778121
Add documentation for anyconst/anyseq/allconst/allseq attribute
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-04-06 14:37:43 +02:00
Clifford Wolf
675dd5347a
Small fixes and improvements in $allconst/$allseq handling
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-26 11:58:44 +01:00
Clifford Wolf
eb67a7532b
Add $allconst and $allseq cell types
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2018-02-23 13:14:47 +01:00
Tim 'mithro' Ansell
19aa261527
Adding COPYING file with license information.
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This allows GitHub and other tools to detect the license info. Providing
a COPYING for LICENSE file is also pretty standard.
2017-10-19 20:22:12 -04:00
Stephen
57b3c34e69
delete bad backslash
2017-09-27 16:52:20 -07:00
Stephen Groat
de0797f073
Add osx tests using brew bundle
2017-09-27 16:49:03 -07:00
Clifford Wolf
a88e019b0c
Merge branch 'master' of https://github.com/stv0g/yosys into stv0g-master
2017-02-11 10:12:17 +01:00
Steffen Vogel
a3f19f047c
Remove space after backslash
2017-02-09 19:08:21 -03:00
Steffen Vogel
94c76f85da
Applied fixes from @joshhead (thanks for your effors!)
2017-02-09 18:53:37 -03:00
Clifford Wolf
848062088c
Add checker support to verilog front-end
2017-02-09 13:51:44 +01:00
Clifford Wolf
ef4a28e112
Add SV "rand" and "const rand" support
2017-02-08 14:38:15 +01:00
Steffen Vogel
b8d531957d
Added notes for compilation on OS X
2017-02-07 11:16:56 -03:00
Clifford Wolf
6abf79eb28
Further improve cover() support
2017-02-04 17:02:13 +01:00
Aleks-Daniel Jakimenko-Aleksejev
3c86da8000
Keep lines under 80 characters
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Recent README changes added some characters to existing lines, which
made them longer than 80 characters. This commit fixes that.
2016-11-19 20:51:50 +02:00
Aleks-Daniel Jakimenko-Aleksejev
751ad3c618
Markdownify README even further
2016-11-19 19:07:02 +02:00
Aleks-Daniel Jakimenko-Aleksejev
d4e1592609
Markdownify README
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This is the first commit in series. There are many other things that
could be improved, this is just the first renderable version.
2016-11-12 23:33:28 +02:00