yosys

Commit Graph

Author	SHA1	Message	Date
Clifford Wolf	137f35373f	Changed more code to dict<> and pool<>	2014-12-28 19:24:24 +01:00
Clifford Wolf	032511fac8	Added functionality to dff2dffe pass	2014-12-08 15:38:58 +01:00
Clifford Wolf	fad9cec47b	Added $_DFFE_??_ cell types	2014-12-08 10:43:38 +01:00
Clifford Wolf	4569a747f8	Renamed SIZE() to GetSize() because of name collision on Win32	2014-10-10 17:07:24 +02:00
Clifford Wolf	c3e779a65f	Added $_BUF_ cell type	2014-10-03 10:12:28 +02:00
Clifford Wolf	af0c8873bb	Added $lcu cell type	2014-09-08 13:31:04 +02:00
Clifford Wolf	d46bac3305	Added "$fa" cell type	2014-09-08 12:15:39 +02:00
Clifford Wolf	b847ec8a0b	Added $macc cell type	2014-09-06 15:47:46 +02:00
Clifford Wolf	8927aa6148	Removed $bu0 cell type	2014-09-04 02:07:52 +02:00
Clifford Wolf	a1c7d4a8e2	Added eval model for $lut cells	2014-08-31 17:43:31 +02:00
Clifford Wolf	4724d94fbc	Added $alu cell type	2014-08-30 18:59:05 +02:00
Clifford Wolf	98442e019d	Added emscripten (emcc) support to build system and some build fixes	2014-08-22 16:20:22 +02:00
Clifford Wolf	47c2637a96	Added additional gate types: $_NAND_ $_NOR_ $_XNOR_ $_AOI3_ $_OAI3_ $_AOI4_ $_OAI4_	2014-08-16 18:29:39 +02:00
Clifford Wolf	56a30cf42c	Added CellTypes::cell_evaluable()	2014-08-16 16:17:07 +02:00
Clifford Wolf	b64b38eea2	Renamed $lut ports to follow A-Y naming scheme	2014-08-15 14:18:40 +02:00
Clifford Wolf	f092b50148	Renamed $_INV_ cell type to $_NOT_	2014-08-15 14:11:40 +02:00
Clifford Wolf	1bf7a18fec	Added module->ports	2014-08-14 16:22:52 +02:00
Clifford Wolf	746aac540b	Refactoring of CellType class	2014-08-14 15:46:51 +02:00
Clifford Wolf	13f2f36884	RIP $safe_pmux	2014-08-14 11:39:46 +02:00
Clifford Wolf	14412e6c95	Preparations for RTLIL::IdString redesign: cleanup of existing code	2014-08-02 00:45:25 +02:00
Clifford Wolf	397b00252d	Added $shift and $shiftx cell types (needed for correct part select behavior)	2014-07-29 16:35:13 +02:00
Clifford Wolf	7bd2d1064f	Using log_assert() instead of assert()	2014-07-28 11:27:48 +02:00
Clifford Wolf	10e5791c5e	Refactoring: Renamed RTLIL::Design::modules to modules_	2014-07-27 11:18:30 +02:00
Clifford Wolf	f9946232ad	Refactoring: Renamed RTLIL::Module::wires to wires_	2014-07-27 01:49:51 +02:00
Clifford Wolf	d4a1b0af5b	Added support for dlatchsr cells	2014-03-31 14:14:40 +02:00
Clifford Wolf	9e99984336	Fixed const folding of $bu0 cells	2014-02-27 04:09:32 +01:00
Clifford Wolf	d85a6bf5d3	Added $slice and $concat to CellTypes list	2014-02-07 19:50:44 +01:00
Clifford Wolf	fc3b3c4ec3	Added $slice and $concat cell types	2014-02-07 17:44:57 +01:00
Clifford Wolf	1e67099b77	Added $assert cell	2014-01-19 14:03:40 +01:00
Clifford Wolf	c69c416d28	Added $bu0 cell (for easy correct $eq/$ne mapping)	2013-12-28 12:02:14 +01:00
Clifford Wolf	369bf81a70	Added support for non-const === and !== (for miter circuits)	2013-12-27 14:20:15 +01:00
Clifford Wolf	e0f693cbb0	Added $_SR_[PN][PN]_, $_DFFSR_[PN][PN][PN]_, $_DLATCH_[PN]_	2013-10-18 12:13:34 +02:00
Clifford Wolf	5998c101a4	Added $sr, $dffsr and $dlatch cell types	2013-10-18 11:56:16 +02:00
Clifford Wolf	ad9bbcbf40	Added $lut cells and abc lut mapping support	2013-07-23 16:19:34 +02:00
Clifford Wolf	6d7b5f9064	Fixed even more ConstEval bugs found using xsthammer	2013-06-14 17:50:26 +02:00
Clifford Wolf	30db70b1ba	Added consteval testing to xsthammer and fixed bugs	2013-06-13 19:51:13 +02:00
Clifford Wolf	ed0e2f7a6f	Added log_assert() api	2013-05-24 14:38:36 +02:00
Clifford Wolf	89f009d171	Added additional functionality and cleanups in sigtools.h and celltypes.h	2013-03-15 10:22:23 +01:00
Clifford Wolf	697cf1eb80	Added #ci and #co selection operators	2013-03-14 15:57:47 +01:00
Clifford Wolf	de823ce964	Added $sr cell type to celltypes.h	2013-03-14 01:08:30 +01:00
Clifford Wolf	65e5e1658c	Added library support to celltypes class and show pass	2013-03-03 10:36:23 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00

42 Commits