riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
10,722 Commits 75 Branches 48 Tags 62 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
Dan Ravensloft 4d9d90079c intel_alm: add additional ABC9 timings 2020-07-23 11:57:07 +01:00
Dan Ravensloft 16a3048308 intel_alm: Documentation improvements 2020-04-21 19:38:15 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00