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yosys
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2 Commits

Author SHA1 Message Date
Miodrag Milanovic acb341745d Fix invalid verilog syntax 2020-03-14 14:33:44 +01:00
whitequark 9ef078848a gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. 2018-12-05 17:13:27 +00:00