riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
12,888 Commits 114 Branches 50 Tags 34 MiB
Commit Graph

12888 Commits

Author SHA1 Message Date
Martin Povišer 10d0e69588 ast/simplify: Make tweaks in advance of big in_lvalue/in_param change 
The following commit will replace the way in_lvalue/in_param is being
tracked in the simplify code. Make tweaks in advance so that it will
be easier to make the old way and the new way agree.

These changes all should be innocuous.
 2023-09-26 13:31:59 +02:00
N. Engelhardt 3319fdc46e show: use dot for wire aliases instead of BUF 2023-09-25 17:20:16 +02:00
Martin Povišer 91bcf81dbd booth: Note down debug prints are broken 2023-09-25 14:51:26 +02:00
Martin Povišer 7179e4f4b8 booth: Improve user interface 2023-09-25 14:50:41 +02:00
Martin Povišer cde2a0b926 booth: Make more use of appropriate helpers 
Use the `addFa` helper, do not misuse `new_id` and make other changes
to the transformation code.
 2023-09-25 14:50:41 +02:00
Martin Povišer d641dfaec2 rtlil: Add helper to emit full-adder cells 2023-09-25 14:50:41 +02:00
Martin Povišer 62302f601d booth: Remove more of unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer 30f8387b75 booth: Rewrite the main cell selection loop 2023-09-25 14:50:41 +02:00
Martin Povišer 986507f95f booth: Streamline the low-level circuit emission 
For the basic single-bit operations, opt for gate cells (`$_AND_` etc.)
instead of the coarse cells (`$and` etc.). For the emission of cells
move to the conventional module methods (`module->addAndGate`) away
from the local helpers. While at it, touch on the surrounding code.
 2023-09-25 14:50:41 +02:00
Martin Povišer cb05262fc4 booth: Remove now-unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer fedd12261f booth: Move away from explicit `Wire` pointers 
To represent intermediate signals use the `SigBit`/`SigSpec` classes as
is customary in the Yosys codebase. Do not pass around `Wire` pointers
unless we have special reason to.
 2023-09-25 14:50:41 +02:00
github-actions[bot] 934c82254d Bump version 2023-09-22 00:14:51 +00:00
Rasmus Munk Larsen 9ed38bf9b6
Speed up the autoname pass by 3x. (#3945) 
* Speed up the autoname pass by 2x. This is accomplished by only constructing IdString objects for plain strings that have a higher score.

* Defer creating IdStrings even further. This increases the speedup to 3x.
 2023-09-21 09:46:49 +00:00
Ethan Mahintorabi aa06809d64 rtlil: Speeds up Yosys by 17% 
This PR speeds up by roughly 17% across a wide spectrum of designs
tested at Google. Particularly for the mux generation pass.

Co-authored-by: Rasmus Larsen <rmlarsen@google.com>
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2023-09-21 10:46:11 +01:00
Rasmus Munk Larsen b9745f638b Remove extraneous "public:". 2023-09-20 16:20:08 -07:00
Rasmus Munk Larsen e0042bdff7 Speed up TopoSort. The main sorting algorithm implementation in TopoSort::sort_worker is 11-12x faster. Overall, the complete sequence of building the graph and sorting is about 2.5-3x faster. The overall impact in e.g. the replace_const_cells optimization pass is a ~25% speedup. End-to-end impact on our synthesis flow is about 3%. 2023-09-20 15:49:05 -07:00
Martin Povišer c4762d930e
Merge pull request #3930 from povik/verific-test-memsemantics 
verific: Add test of accurate semantics in memory inference
 2023-09-20 11:46:42 +02:00
Martin Povišer 99a5773911
Merge pull request #3920 from zachjs/asgn-expr 
sv: support assignments within expressions
 2023-09-20 11:30:14 +02:00
github-actions[bot] 35a05686c4 Bump version 2023-09-20 00:15:04 +00:00
Miodrag Milanović 8fb807cd24
Merge pull request #3943 from YosysHQ/verific_lineinfo 
Set src attribute for verific with full info
 2023-09-19 12:55:43 +02:00
Miodrag Milanovic 18855f23ce Set src attribute for verific with full info 2023-09-19 12:00:10 +02:00
Zachary Snow 28e99f2b8c fix width of post-increment/decrement expressions 2023-09-18 23:46:06 -04:00
Zachary Snow 7d07615dee allow attributes in front of ++/-- statements 2023-09-18 23:46:02 -04:00
github-actions[bot] e2b613355d Bump version 2023-09-19 00:23:00 +00:00
Martin Povišer 54be4aca90
Merge pull request #3924 from andyfox-rushc/master 
multpass -- create Booth Encoded multipliers for
 2023-09-18 16:46:59 +02:00
Martin Povišer 8222121164 verific: Add test of accurate semantics in memory inference 2023-09-18 16:37:15 +02:00
N. Engelhardt 6dc7cc3a0e
Merge pull request #3933 from timkpaine/tkp/kernelheaders 2023-09-18 16:29:51 +02:00
N. Engelhardt 39dc2c0725
Merge pull request #3925 from povik/ci-glibcxx-assertions 2023-09-18 16:11:04 +02:00
Tim Paine 9042124ba7 Alphabetize headers to be installed, include some missing required ones for plugins, fixes https://github.com/chipsalliance/synlig/pull/1972 https://github.com/dau-dev/tools/issues/6 2023-09-15 14:31:08 -04:00
github-actions[bot] b84ed5d3ad Bump version 2023-09-14 00:14:42 +00:00
Catherine c7d7cfeaca Update ABC for WASI support. 2023-09-13 16:43:30 +01:00
Miodrag Milanović eada408983
Merge pull request #3931 from whitequark/update-abc 
Update ABC for WASI support
 2023-09-13 13:40:49 +02:00
Miodrag Milanović d79b4b2218
Merge pull request #3903 from jix/dft-future_ff 
Basic support for tag primitives and `$future_ff`
 2023-09-13 13:40:10 +02:00
Catherine e9a11dd088 Update ABC for WASI support. 2023-09-13 11:39:30 +00:00
Jannis Harder 0e8a4adb59 verific: Update YOSYSHQ_VERIFIC_API_VERSION 2023-09-13 11:32:36 +02:00
Jannis Harder 62b4df4989 dft_tag: Implement `$overwrite_tag` and `$original_tag` 
This does not correctly handle an `$overwrite_tag` on a module output,
but since we currently require the user to flatten the design for
cross-module dft, this cannot be observed from within the design, only
by manually inspecting the signals in the design.
 2023-09-13 11:32:36 +02:00
Jannis Harder 78ff40d1b2 Run `future` as part of `prep` 2023-09-13 11:32:36 +02:00
Jannis Harder 46a35da28c Add `future` pass to resolve `$future_ff` cells 2023-09-13 11:32:36 +02:00
Jannis Harder 7a0c37b62d Initial dft_tag implementation 
This is still missing a mode to rewrite $overwrite_tag and $original_tag
by injecting $set_tag and $get_tag in the right places. It's also
missing bit-precise propagation models for shifts and arithmetic and
requires the design to be flattened.
 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 27ac912709 Support import of $future_ff 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 9c255c98b1 unescape string tag attribute 2023-09-13 11:32:36 +02:00
Miodrag Milanovic 54050a8c16 Basic support for tag primitives 2023-09-13 11:32:36 +02:00
github-actions[bot] 9e004426e0 Bump version 2023-09-13 00:14:55 +00:00
Martin Povišer 08f79d111e ci: Enable extra libstdc++ assertions 2023-09-12 19:45:07 +02:00
Martin Povišer 05f0262d77
Merge pull request #3929 from YosysHQ/gatecat/fmt-fix 
fmt: Fix C++ string assertion when buf is empty
 2023-09-12 19:44:17 +02:00
Martin Povišer b04f2352bb
Merge pull request #3928 from povik/mem-wr-merge-transpemu-fix 
mem: Fix index confusion in write port merging
 2023-09-12 19:43:58 +02:00
gatecat 98b9459535 fmt: Fix C++ string assertion when buf is empty 
Signed-off-by: gatecat <gatecat@ds0.me>
 2023-09-12 18:12:07 +02:00
Martin Povišer cbc4ec8178 mem: Fix index confusion in write port merging 
Fix mistaking the read-port and write-port indices for each other when
we are adding the partial transparency emulation to be able to merge two
write ports.
 2023-09-12 16:43:59 +02:00
Miodrag Milanović 88ce47e4f0
Merge pull request #3892 from QuantamHD/dont_use 
abc: Exposes dont_use flag in ABC
 2023-09-12 14:58:44 +02:00
Miodrag Milanović 1b5c7b8dd7
Merge pull request #3927 from YosysHQ/verific_memory 
verific - respect order of read and write for rams
 2023-09-12 14:58:02 +02:00