Clifford Wolf
|
a923a63a89
|
Ignore celldefine directive in verilog front-end
|
2015-03-25 19:46:12 +01:00 |
Clifford Wolf
|
1f1deda888
|
Added non-std verilog assume() statement
|
2015-02-26 18:47:39 +01:00 |
Clifford Wolf
|
ef151b0b30
|
Fixed handling of "//" in filenames in verilog pre-processor
|
2015-02-14 08:41:03 +01:00 |
Clifford Wolf
|
df9d096a7d
|
Ignoring more system task and functions
|
2015-01-15 13:08:19 +01:00 |
Clifford Wolf
|
7751c491fb
|
Improved some warning messages
|
2014-12-27 03:40:27 +01:00 |
Clifford Wolf
|
76c83283c4
|
Fixed minor bug in parsing delays
|
2014-11-24 14:48:07 +01:00 |
Clifford Wolf
|
56c7d1e266
|
Fixed two minor bugs in constant parsing
|
2014-11-24 14:39:24 +01:00 |
Clifford Wolf
|
fe829bdbdc
|
Added log_warning() API
|
2014-11-09 10:44:23 +01:00 |
Clifford Wolf
|
c5eb5e56b8
|
Re-introduced Yosys::readsome() helper function
(f.read() + f.gcount() made problems with lines > 16kB)
|
2014-10-23 10:58:36 +02:00 |
William Speirs
|
fad0b0c506
|
Updated lexers & parsers to include prefixes
|
2014-10-15 00:48:19 +02:00 |