6 Commits

Author	SHA1	Message	Date
Miodrag Milanovic	50ef4561d4	Fix cells_sim.v for Achronix FPGA	2019-01-04 15:15:23 +01:00
whitequark	efa278e232	Fix typographical and grammatical errors and inconsistencies. ... The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.	2019-01-02 13:12:17 +00:00
c60k28	efed2420d6	Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal value for the POWER_UP parameter. Fixed and tested Cyclone V device	2018-03-31 22:48:47 -06:00
Larry Doolittle	efaef82f75	Squelch trailing whitespace, including meta-whitespace	2018-03-11 16:03:41 +01:00
dh73	1fc061d90c	Organizing Speedster file names	2017-11-08 20:23:55 -06:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00