This website requires JavaScript.
Explore
Help
Sign In
riscv
/
yosys
mirror of
https://github.com/YosysHQ/yosys.git
Watch
1
Star
0
Fork
You've already forked yosys
0
Code
Issues
Projects
Releases
Wiki
Activity
12,806
Commits
75
Branches
48
Tags
60
MiB
d71dd5b9bb
Commit Graph
1 Commits
Author
SHA1
Message
Date
Zachary Snow
15a4e900b2
verilog: support for time scale delay values
2022-02-14 15:58:31 +01:00