Clifford Wolf
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b7dda72302
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
|
cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
Clifford Wolf
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2bec47a404
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Use only module->addCell() and module->remove() to create and delete cells
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2014-07-25 17:56:19 +02:00 |
Clifford Wolf
|
4b4048bc5f
|
SigSpec refactoring: using the accessor functions everywhere
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
765f172211
|
Changes to "memory" pass for new $memwr/$mem WR_EN interface
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2014-07-16 12:49:50 +02:00 |
Clifford Wolf
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a6750b3753
|
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
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2014-02-03 13:01:45 +01:00 |
Clifford Wolf
|
67b0ce2578
|
Only generate write-enable $and if WE is not constant 1 in memory_map
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2014-02-02 21:27:26 +01:00 |
Clifford Wolf
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93a70959f3
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Replaced RTLIL::Const::str with generic decoder method
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2013-12-04 14:14:05 +01:00 |
Clifford Wolf
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95dbacefbf
|
Fixed bug in synthesis of memories that are never written
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2013-10-17 21:00:37 +02:00 |
Clifford Wolf
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f3a849512f
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Added help messages to memory_* passes
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2013-03-01 10:17:35 +01:00 |
Clifford Wolf
|
7764d0ba1d
|
initial import
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2013-01-05 11:13:26 +01:00 |