riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
11,699 Commits 75 Branches 48 Tags 60 MiB
Commit Graph

6 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 77b1dfd8c3 opt_mem: Remove constant-value bit lanes. 2022-05-07 23:13:16 +02:00
Claire Xenia Wolf d6e4d3f1ba Fix the tests we just broke 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-12-10 00:22:37 +01:00
Xiretza acd47bbd52
tests: Centralize test collection and Makefile generation 2020-09-21 15:07:02 +02:00
Clifford Wolf bada3ee815 Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh 2014-03-11 11:59:58 +01:00
Clifford Wolf 4fd1a4c12b Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog) 2014-03-11 11:39:30 +01:00
Clifford Wolf 81b3f52519 Added tests/techmap/mem_simple_4x1 2014-02-21 12:06:40 +01:00