8 Commits

Author	SHA1	Message	Date
Eddie Hung	fce8dc7db2	Add test	2019-08-20 20:05:16 -07:00
Clifford Wolf	924d9d6e86	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
Clifford Wolf	dcf2e24240	Added $meminit support to "memory" command	2015-02-14 12:55:03 +01:00
Clifford Wolf	73a345294a	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	2014-07-16 14:08:51 +02:00
Clifford Wolf	bada3ee815	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	2014-03-11 11:59:58 +01:00
Clifford Wolf	4fd1a4c12b	Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)	2014-03-11 11:39:30 +01:00
Clifford Wolf	3c5e973092	Use private namespace in mem_simple_4x1_map	2014-02-21 12:14:38 +01:00
Clifford Wolf	81b3f52519	Added tests/techmap/mem_simple_4x1	2014-02-21 12:06:40 +01:00