yosys

Commit Graph

Author	SHA1	Message	Date
Emil J. Tywoniak	785bd44da7	rtlil: represent Const strings as std::string	2024-10-14 06:28:12 +02:00
Martin Povišer	030d639201	opt_mem, memory_*: Refuse to operate in presence of processes Processes can contain `MemWriteAction` entries which are invisible to most passes operating on memories but which will be lowered to write ports later on by `proc_memwr`. For that reason we can get corrupted RTLIL if we sequence the memory passes before `proc`. Address that by making the affected memory passes ignore modules with processes.	2024-02-23 12:27:53 +01:00
uis	5902b2826d	Fix printf formats	2024-01-15 12:07:54 +01:00
N. Engelhardt	080da693d1	memory_libmap: update search order for attributes	2023-10-24 13:55:45 +02:00
N. Engelhardt	1b6d1e9419	memory_libmap: look for ram_style attributes on surrounding signals	2023-10-19 19:23:35 +02:00
Martin Povišer	3de84b959f	memory_libmap: Tweak whitespace	2023-09-04 17:38:35 +02:00
N. Engelhardt	57de249881	memory_libmap: print additional debug messages when no valid mapping is found	2023-07-06 18:54:32 +02:00
N. Engelhardt	a6be7b4751	memory_libmap: add debug messages for some reasons for rejecting mappings	2023-06-29 14:08:31 +02:00
N. Engelhardt	7542146fc5	memory_libmap: print message about attributes forcing ram kind	2023-06-28 17:48:20 +02:00
Marcelina Kościelnicka	d69091806a	memory_libmap: Fix wrprio handling.	2022-06-17 02:09:37 +02:00
Marcelina Kościelnicka	25a4cd7020	memory_libmap: Fix params emitted for unused ports for consistency.	2022-06-16 08:14:08 +02:00
Marcelina Kościelnicka	3a0aa9c663	memory_dff: Add support for no_rw_check attribute.	2022-06-02 12:49:34 +02:00
Marcelina Kościelnicka	7c5dba8b77	Add memory_libmap pass.	2022-05-18 17:32:56 +02:00

13 Commits