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13258 Commits

Author SHA1 Message Date
Miodrag Milanovic 46838172c2 Next dev cycle 2024-02-09 08:19:14 +01:00
Miodrag Milanovic 543faed9c8 Release version 0.38 2024-02-09 08:16:24 +01:00
github-actions[bot] 8e3a718e30 Bump version 2024-02-09 00:15:19 +00:00
Miodrag Milanović 2f4c917dac
Merge pull request #4181 from povik/ci-cxxstd-fix 
ci: Fix CXXSTD typo
 2024-02-08 18:55:47 +01:00
Miodrag Milanović d808258583
Merge pull request #4193 from povik/opt_lut-help 
opt_lut: Remove leftover `-dlogic` help
 2024-02-08 18:54:16 +01:00
Martin Povišer 043f1e2bcb opt_lut: Remove leftover `-dlogic` help 2024-02-08 17:49:44 +01:00
Martin Povišer af1a5cfeb9 Address `SigBit`/`SigSpec` confusion issues under c++20 2024-02-08 17:48:36 +01:00
Martin Povišer 66479a2232 hashlib: Add missing `stdint.h` include 
We use `uint32_t` `uint64_t` etc. so add an explicit include.
 2024-02-08 14:27:12 +00:00
Catherine 1236bb65b6 read_verilog: don't include empty `opt_sva_label` in span. 
Consider this SystemVerilog file:

    module top(...);
      input clk;
      input [7:0] data;
      input ack;

      always @(posedge clk)
        if (ack) begin
          assert(data != 8'h0a);
        end
    endmodule

Before this commit, the span for the assert was:

        if (ack) begin>
          assert(data != 8'h0a)<;

After this commit, the span for the assert is:

        if (ack) begin
          >assert(data != 8'h0a)<;

This helps editor integrations that only look at the beginning
of the span.
 2024-02-08 14:25:35 +00:00
Miodrag Milanović 675b8a7319
Merge pull request #4190 from YosysHQ/xdg 
Follow the XDG Base Directory Specification
 2024-02-08 14:05:31 +01:00
Miodrag Milanovic a38273c19d add log_suppressed and fixed formatting 2024-02-08 12:19:42 +01:00
Martin Povišer a1824ba5b6
Merge pull request #4187 from povik/synth-help 
synth: Run script in full in help mode
 2024-02-08 09:56:48 +01:00
Miodrag Milanovic 2797d67569 Move block and change message to debug 2024-02-08 09:19:19 +01:00
Miodrag Milanovic f785eef685 Merge branch 'master' of github.com:hakan-demirli/yosys into xdg 2024-02-08 09:03:52 +01:00
Martin Povišer 862f2fd705 proc_dlatch: Include `$bwmux` among considered mux cells 2024-02-08 00:08:50 +01:00
Martin Povišer 7a3316dd78 synth: Tweak phrasing of `-booth` help 2024-02-08 00:05:15 +01:00
Martin Povišer a98d363d9d synth: Run script in full in help mode 2024-02-08 00:05:15 +01:00
github-actions[bot] 16ff3e0a30 Bump version 2024-02-07 00:14:46 +00:00
Jannis Harder 364bcfb8f1 Example pass for the scopeinfo index/lookup utils 2024-02-06 18:01:26 +01:00
Jannis Harder 0d5b48de98 Add scopeinfo index/lookup utils 2024-02-06 18:01:26 +01:00
Jannis Harder bbe39762ad Ignore $scopeinfo in write_json 2024-02-06 17:51:29 +01:00
Jannis Harder f31fb95963 Ignore $scopeinfo in write_verilog 2024-02-06 17:51:29 +01:00
Jannis Harder 5ee8bebde4 Ignore $scopeinfo in write_spice 2024-02-06 17:51:29 +01:00
Jannis Harder 418bf61b8d Ignore $scopeinfo in write_smv 2024-02-06 17:51:29 +01:00
Jannis Harder 55d8425468 Ignore $scopeinfo in write_firrtl 2024-02-06 17:51:29 +01:00
Jannis Harder 59a60c76fe Ignore $scopeinfo in write_blif 2024-02-06 17:51:29 +01:00
Jannis Harder 5cfbc1604c Ignore $scopeinfo in write_edif 2024-02-06 17:51:29 +01:00
Jannis Harder 10d5d358d2 Ignore $scopeinfo in write_aiger 
While SBY's aiger flow already removes non-assertion driving logic,
there are some uses of write_aiger outside of SBY that could end up with
$scopeinfo cells, so we explicitly ignore them.

The write_btor backend works differently and due to the way it
recursively visits cells, it would never reach isolated cells like
$scopeinfo.
 2024-02-06 17:51:29 +01:00
Jannis Harder bfd9cf63db Ignore $scopeinfo in opt_merge 2024-02-06 17:51:29 +01:00
Jannis Harder 9288107f43 Test flatten and opt_clean's $scopeinfo handling 2024-02-06 17:51:29 +01:00
Jannis Harder 8902fc94b6 Suport $scopeinfo in flatten and opt_clean 2024-02-06 17:51:29 +01:00
Jannis Harder f728927307 Add builtin celltype $scopeinfo 
Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
 2024-02-06 17:51:24 +01:00
Miodrag Milanović 269c50f90e
Merge pull request #4130 from jix/hierarchy-defer-notop 
hierarchy: Without a known top module, derive all deferred modules
 2024-02-06 12:08:01 +01:00
Miodrag Milanovic d00843d436 Add -nordff to test 2024-02-06 10:36:30 +01:00
Jannis Harder 0470cbb00d hierarchy: Without a known top module, derive all deferred modules 
This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
 2024-02-06 10:31:40 +01:00
Miodrag Milanović 5d3e4c5c7a
Merge pull request #4182 from QuantamHD/fix_aldff 
verific: Improves aldff inference in verific importer
 2024-02-06 08:19:43 +01:00
github-actions[bot] 1df2a209e5 Bump version 2024-02-06 00:15:26 +00:00
Claire Xen 1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite 
Add API to overwrite existing pass from plugin
 2024-02-05 23:49:24 +01:00
Martin Povišer 57db87c99f py_wrap_generator: Handle const-qualified callbacks 2024-02-05 17:25:55 +01:00
N. Engelhardt 2422dd6845
Merge pull request #4153 from Coloquinte/blif_delay_constraints 
Issue a warning instead of a syntax error for blif delay constraints
 2024-02-05 15:14:05 +01:00
N. Engelhardt f96e27ac14
Merge pull request #4123 from povik/clean-opt_clean 
opt_clean: Add commentary, remove dead code
 2024-02-05 15:08:34 +01:00
Ethan Mahintorabi ff578ecabd
fix formatting 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:23:04 +00:00
Ethan Mahintorabi bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer 
The following SV module at HEAD imported with verific,

```systemverilog
    module my_module(
      input logic [4:0] a,
      input logic clk,
      input logic enable,
      output logic [4:0] z
    );

    reg [4:0] pipeline_register;
    always @(posedge clk) begin
      pipeline_register <= enable ? a : pipeline_register;
    end
    assign z = pipeline_register;

    endmodule : my_module

```

results in the following output verilog

```systemverilog
/* Generated by 0.36 */

(* top =  1  *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
  wire [4:0] _0_;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
  input [4:0] a;
  wire [4:0] a;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
  input clk;
  wire clk;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
  input enable;
  wire enable;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
  output [4:0] z;
  wire [4:0] z;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
  \$aldff  #(
    .ALOAD_POLARITY(32'd1),
    .CLK_POLARITY(32'd1),
    .WIDTH(32'd5)
  ) _1_ (
    .AD(5'hxx),
    .ALOAD(1'h0),
    .CLK(clk),
    .D(_0_),
    .Q(z)
  );
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
  \$mux  #(
    .WIDTH(32'd5)
  ) _2_ (
    .A(z),
    .B(a),
    .S(enable),
    .Y(_0_)
  );
endmodule
```

Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.

My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:10:25 +00:00
Krystine Sherwin 0cdd4273b4
ci: ignore yosys-config return code 2024-02-05 15:41:50 +13:00
Krystine Sherwin 9eed04dd4b
Docs: Note on debug for memory_libmap 2024-02-05 15:38:01 +13:00
Martin Povišer 97b8ee5ab9 ci: Get a dump of yosys-config into the build log 2024-02-04 23:29:46 +01:00
Martin Povišer 3f457f2388 ci: Fix CXXSTD typo 2024-02-04 23:21:06 +01:00
github-actions[bot] f5420d720c Bump version 2024-02-04 00:17:08 +00:00
Catherine 3caac53827
Merge pull request #4128 from whitequark/check-cell 
Add `$check` cell to represent assertions with messages
 2024-02-03 18:39:00 +00:00
Jannis Harder ffb82df33c Additional tests for FV $check compatibility 2024-02-02 16:07:10 +01:00