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Merge pull request #4182 from QuantamHD/fix_aldff 

verific: Improves aldff inference in verific importer
This commit is contained in:
Miodrag Milanović 2024-02-06 08:19:43 +01:00 committed by GitHub
parent 1df2a209e5 ff578ecabd
commit 5d3e4c5c7a
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GPG Key ID: B5690EEEBB952194
2 changed files with 26 additions and 15 deletions
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40
frontends/verific/verific.cc
View File

@ -343,36 +343,46 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
}
}
RTLIL::SigBit VerificImporter::netToSigBit(Verific::Net *net) {
if (net && net->IsGnd())
return RTLIL::State::S0;
else if (net && net->IsPwr())
return RTLIL::State::S1;
else if (net && net->IsX())
return RTLIL::State::Sx;
else if (net)
return net_map_at(net);
else
return RTLIL::State::Sz;
}
RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst)
{
RTLIL::SigSpec sig;
for (int i = int(inst->InputSize())-1; i >= 0; i--)
if (inst->GetInputBit(i))
sig.append(net_map_at(inst->GetInputBit(i)));
else
sig.append(RTLIL::State::Sz);
for (int i = int(inst->InputSize())-1; i >= 0; i--) {
Net *net = inst->GetInputBit(i);
sig.append(netToSigBit(net));
}
return sig;
}
RTLIL::SigSpec VerificImporter::operatorInput1(Instance *inst)
{
RTLIL::SigSpec sig;
for (int i = int(inst->Input1Size())-1; i >= 0; i--)
if (inst->GetInput1Bit(i))
sig.append(net_map_at(inst->GetInput1Bit(i)));
else
sig.append(RTLIL::State::Sz);
for (int i = int(inst->Input1Size())-1; i >= 0; i--) {
Net *net = inst->GetInput1Bit(i);
sig.append(netToSigBit(net));
}
return sig;
}
RTLIL::SigSpec VerificImporter::operatorInput2(Instance *inst)
{
RTLIL::SigSpec sig;
for (int i = int(inst->Input2Size())-1; i >= 0; i--)
if (inst->GetInput2Bit(i))
sig.append(net_map_at(inst->GetInput2Bit(i)));
else
sig.append(RTLIL::State::Sz);
for (int i = int(inst->Input2Size())-1; i >= 0; i--) {
Net *net = inst->GetInput2Bit(i);
sig.append(netToSigBit(net));
}
return sig;
}

1
frontends/verific/verific.h
View File

@ -83,6 +83,7 @@ struct VerificImporter
RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr);
RTLIL::SigBit netToSigBit(Verific::Net *net);
RTLIL::SigSpec operatorInput(Verific::Instance *inst);
RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
RTLIL::SigSpec operatorInput2(Verific::Instance *inst);