Clifford Wolf
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584d2030bf
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Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-03-29 16:32:44 +01:00 |
Clifford Wolf
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ddc1761f1a
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Add "make coverage"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2018-08-27 14:22:21 +02:00 |
Clifford Wolf
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e4ef000b70
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Adjust makefiles to work with out-of-tree builds
This is based on work done by Larry Doolittle
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2015-08-12 15:04:44 +02:00 |
Fabio Utzig
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fff6f00b3c
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Enable bison to be customized
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2015-01-08 09:56:20 -02:00 |
William Speirs
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fad0b0c506
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Updated lexers & parsers to include prefixes
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2014-10-15 00:48:19 +02:00 |
Clifford Wolf
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b17d6531c8
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Added "make PRETTY=1"
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2014-07-24 17:15:01 +02:00 |
Clifford Wolf
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4a4a3fc337
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Various improvements in support for generate statements
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2013-12-04 21:06:54 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |