riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
7,482 Commits 85 Branches 48 Tags 37 MiB
Commit Graph

5 Commits

Author SHA1 Message Date
Miodrag Milanovic 8badd4d812 better handling of lut and begin/end add 2019-09-18 17:45:07 +02:00
Miodrag Milanovic 3487b95224 Added simulation models for Efinix and Anlogic 2019-09-15 09:37:16 +02:00
Miodrag Milanovic cf96f41c6d Added bram support 2019-08-04 11:46:36 +02:00
Miodrag Milanovic 6e210f26fa Custom step to add global clock buffers 2019-08-03 14:40:23 +02:00
Miodrag Milanovic ab98f604fd Initial EFINIX support 2019-08-03 13:10:44 +02:00