bbe39762ad
Ignore $scopeinfo in write_json
2024-02-06 17:51:29 +01:00
f31fb95963
Ignore $scopeinfo in write_verilog
2024-02-06 17:51:29 +01:00
5ee8bebde4
Ignore $scopeinfo in write_spice
2024-02-06 17:51:29 +01:00
418bf61b8d
Ignore $scopeinfo in write_smv
2024-02-06 17:51:29 +01:00
55d8425468
Ignore $scopeinfo in write_firrtl
2024-02-06 17:51:29 +01:00
59a60c76fe
Ignore $scopeinfo in write_blif
2024-02-06 17:51:29 +01:00
5cfbc1604c
Ignore $scopeinfo in write_edif
2024-02-06 17:51:29 +01:00
10d5d358d2
Ignore $scopeinfo in write_aiger
...
While SBY's aiger flow already removes non-assertion driving logic,
there are some uses of write_aiger outside of SBY that could end up with
$scopeinfo cells, so we explicitly ignore them.
The write_btor backend works differently and due to the way it
recursively visits cells, it would never reach isolated cells like
$scopeinfo.
2024-02-06 17:51:29 +01:00
bfd9cf63db
Ignore $scopeinfo in opt_merge
2024-02-06 17:51:29 +01:00
9288107f43
Test flatten and opt_clean's $scopeinfo handling
2024-02-06 17:51:29 +01:00
8902fc94b6
Suport $scopeinfo in flatten and opt_clean
2024-02-06 17:51:29 +01:00
f728927307
Add builtin celltype $scopeinfo
...
Only declares the cell interface, doesn't make anything use or
understand $scopeinfo yet.
2024-02-06 17:51:24 +01:00
269c50f90e
Merge pull request #4130 from jix/hierarchy-defer-notop
...
hierarchy: Without a known top module, derive all deferred modules
2024-02-06 12:08:01 +01:00
d00843d436
Add -nordff to test
2024-02-06 10:36:30 +01:00
0470cbb00d
hierarchy: Without a known top module, derive all deferred modules
...
This fixes hierarchy when used with cell libraries that were loaded with
-defer and also makes more of the hierarchy visible to the auto-top
heuristic.
2024-02-06 10:31:40 +01:00
5d3e4c5c7a
Merge pull request #4182 from QuantamHD/fix_aldff
...
verific: Improves aldff inference in verific importer
2024-02-06 08:19:43 +01:00
1df2a209e5
Bump version
2024-02-06 00:15:26 +00:00
1b73b5beb7
Merge pull request #4174 from YosysHQ/claire/overwrite
...
Add API to overwrite existing pass from plugin
2024-02-05 23:49:24 +01:00
57db87c99f
py_wrap_generator: Handle const-qualified callbacks
2024-02-05 17:25:55 +01:00
2422dd6845
Merge pull request #4153 from Coloquinte/blif_delay_constraints
...
Issue a warning instead of a syntax error for blif delay constraints
2024-02-05 15:14:05 +01:00
f96e27ac14
Merge pull request #4123 from povik/clean-opt_clean
...
opt_clean: Add commentary, remove dead code
2024-02-05 15:08:34 +01:00
ff578ecabd
fix formatting
...
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-05 07:23:04 +00:00
bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer
...
The following SV module at HEAD imported with verific,
```systemverilog
module my_module(
input logic [4:0] a,
input logic clk,
input logic enable,
output logic [4:0] z
);
reg [4:0] pipeline_register;
always @(posedge clk) begin
pipeline_register <= enable ? a : pipeline_register;
end
assign z = pipeline_register;
endmodule : my_module
```
results in the following output verilog
```systemverilog
/* Generated by 0.36 */
(* top = 1 *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
wire [4:0] _0_;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
input [4:0] a;
wire [4:0] a;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
input clk;
wire clk;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
input enable;
wire enable;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
output [4:0] z;
wire [4:0] z;
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
\$aldff #(
.ALOAD_POLARITY(32'd1),
.CLK_POLARITY(32'd1),
.WIDTH(32'd5)
) _1_ (
.AD(5'hxx),
.ALOAD(1'h0),
.CLK(clk),
.D(_0_),
.Q(z)
);
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
\$mux #(
.WIDTH(32'd5)
) _2_ (
.A(z),
.B(a),
.S(enable),
.Y(_0_)
);
endmodule
```
Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.
My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
2024-02-05 07:10:25 +00:00
0cdd4273b4
ci: ignore yosys-config return code
2024-02-05 15:41:50 +13:00
9eed04dd4b
Docs: Note on debug for memory_libmap
2024-02-05 15:38:01 +13:00
97b8ee5ab9
ci: Get a dump of yosys-config into the build log
2024-02-04 23:29:46 +01:00
3f457f2388
ci: Fix CXXSTD typo
2024-02-04 23:21:06 +01:00
f5420d720c
Bump version
2024-02-04 00:17:08 +00:00
3caac53827
Merge pull request #4128 from whitequark/check-cell
...
Add `$check` cell to represent assertions with messages
2024-02-03 18:39:00 +00:00
ffb82df33c
Additional tests for FV $check compatibility
2024-02-02 16:07:10 +01:00
7dbe288d6f
fix: descriptive logs
2024-02-02 02:39:04 +03:00
c1d3288654
chore: use similar variable/function names
2024-02-02 01:25:58 +03:00
c7bf0e3b8f
Add new `$check` cell to represent assertions with a message.
2024-02-01 20:10:39 +01:00
e1a59ba80b
async2sync, clk2fflogic: Add support for $check and $print cells
2024-02-01 20:10:39 +01:00
6c4902313b
chformal: Support $check cells and add chformal -lower
...
This adds support for `$check` cells in chformal and adds a `-lower`
mode which converts `$check` cells into `$assert` etc. cells with a
`$print` cell to output the `$check` message.
2024-02-01 20:10:39 +01:00
331ac5285f
tests: Run async2sync before sat and/or sim to handle $check cells
...
Right now neither `sat` nor `sim` have support for the `$check` cell.
For formal verification it is a good idea to always run either
async2sync or clk2fflogic which will (in a future commit) lower `$check`
to `$assert`, etc.
While `sim` should eventually support `$check` directly, using
`async2sync` is ok for the current tests that use `sim`, so this commit
also runs `async2sync` before running sim on designs containing
assertions.
2024-02-01 16:14:11 +01:00
2baa578d94
Remove too fragile smtlib2_module test
...
This compares the write_smt2 output pretty much verbatim, which contains
auto generated private names and fixes an arbitrary ordering. The tested
functionality is also covered by SBY tests which actually interpret the
write_smt2 output using an SMT solver and thus are much more robust, so
we can safely remove this test.
2024-02-01 16:14:11 +01:00
9f27923782
Merge pull request #4173 from YosysHQ/verific_complex
...
verific: add option to skip simplifying complex ports
2024-02-01 12:08:40 +01:00
a84fa0a277
connect: Do interpret selection arguments
...
Instead of silently ignoring what would ordinarily be the selection
arguments to a pass, interpret those and mark the support in the help
message.
2024-02-01 10:28:36 +01:00
bbb8ad5997
Bump version
2024-02-01 00:16:28 +00:00
dd5dc06863
fix: save history file on windows
2024-01-31 20:14:32 +03:00
820232eaca
fix: function naming and locations
2024-01-31 19:50:31 +03:00
6c4bc5aae5
Merge pull request #4165 from phsauter/shiftadd-offset-fix
...
peepopt: handle offset too large in `shiftadd`
2024-01-31 13:47:39 +01:00
cbdf9b2f9c
peepopt: handle empty src-attribute in shiftadd
2024-01-31 13:07:01 +01:00
3bc83c6533
Bump version
2024-01-31 00:15:44 +00:00
8c731658c2
Merge branch 'YosysHQ:master' into master
2024-01-31 01:03:59 +03:00
039634d973
feat: mkdir with tree
2024-01-31 01:03:01 +03:00
4fa314c0bd
Add API to overwrite existing pass from plugin
...
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
2024-01-30 17:51:11 +01:00
db1de5fe5d
verific: add option to skip simplifying complex ports
2024-01-30 16:33:44 +01:00
3537976477
Merge pull request #4163 from QuantamHD/fix_write_verilog
...
write_verilog: Making sure BUF cells are converted to expressions.
2024-01-30 10:58:42 +01:00
Jannis Harder
Miodrag Milanović
github-actions[bot]
Claire Xen
Martin Povišer
N. Engelhardt
Ethan Mahintorabi
Krystine Sherwin
Catherine
hakan-demirli
Philippe Sauter
hakan-demirli