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2 Commits

Author SHA1 Message Date
Claire Xenia Wolf 15fb0107dc Fix "make vgtest" so it runs to the end (but now it fails ;) 
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
 2021-09-23 14:54:28 +02:00
Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks 
This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
 2021-02-07 11:48:39 -05:00