Patrick Urban
2c7ba0e752
gatemate: Enable register initialization
2023-02-15 17:29:01 +01:00
Jannis Harder
1c667fab2b
Merge pull request #3672 from jix/yw-cosim-hierarchy-fixes
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sim: For yw cosim, drive parent module's signals for input ports
2023-02-15 13:45:00 +01:00
Jannis Harder
1cedad7a68
Merge pull request #3675 from daglem/struct-item-queries
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Support for data and array queries on struct/union item expressions
2023-02-15 13:33:34 +01:00
Jannis Harder
68480dfa19
Merge pull request #3671 from zachjs/master
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Add test for typenames using constants shadowed later on
2023-02-15 13:04:43 +01:00
N. Engelhardt
b562b54c14
dfflegalize: allow setting mince and minsrst args from scratchpad
2023-02-15 12:53:46 +01:00
Dag Lem
f8219289b2
Corrected tests for data and array queries on struct/union item expressions
2023-02-15 12:36:29 +01:00
Dag Lem
c1e12877f0
Support for data and array queries on struct/union item expressions
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For now, $bits, $left, $right, $low, $high, and $size are supported.
2023-02-15 11:44:24 +01:00
Jannis Harder
53bda9de54
Merge pull request #3661 from daglem/struct-array-range-offset
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Handle range offsets in packed arrays within packed structs
2023-02-15 11:21:56 +01:00
github-actions[bot]
59de4a0e7f
Bump version
2023-02-15 00:17:48 +00:00
Jannis Harder
ec94703619
Merge pull request #2995 from georgerennie/cover_precond
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chformal: Add -coverenable option
2023-02-14 17:46:31 +01:00
Jannis Harder
85f611fb23
Merge pull request #3126 from georgerennie/equiv_make_assertions
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equiv_make: Add -make_assert option
2023-02-14 17:15:55 +01:00
Jannis Harder
b636af9751
chformal: Note about using -coverenable with the Verific frontend
2023-02-14 17:10:43 +01:00
Patrick Urban
f37073050b
gatemate: Update CC_PLL parameters
2023-02-14 12:02:41 +01:00
Patrick Urban
6a7d5257cd
gatemate: Add CC_USR_RSTN primitive
2023-02-14 12:02:41 +01:00
Patrick Urban
4cb27b1a3a
gatemate: Ensure compatibility of LVDS ports with VHDL
2023-02-14 12:02:41 +01:00
github-actions[bot]
e0bc25f1af
Bump version
2023-02-14 00:17:45 +00:00
Jannis Harder
d2032ac6fd
Merge pull request #3669 from jix/fix-xprop-tests-yosys-call
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tests: Fix path of yosys invocation in xprop tests
2023-02-13 17:55:36 +01:00
Miodrag Milanovic
550a5b7b6b
Update license
2023-02-13 17:23:26 +01:00
Miodrag Milanovic
713b7d3e26
added support for latched output reset
2023-02-13 17:23:26 +01:00
Miodrag Milanovic
131b557727
Initial implementation of synthesizable assertions
2023-02-13 17:23:26 +01:00
Jannis Harder
55ad3fe6c7
xprop tests: Make iverilog invocation more portable
2023-02-13 16:54:11 +01:00
Jannis Harder
2a68eee5f1
xprop: Test fixes and abort on test failure
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Use `$finish(0)` to silently exit even when using recent iverlog
versions. Run `write_verilog -noexpr` before `write_verilog` as the
latter can modify the design.
This also enables checking the tests results, as xprop should be in a
state where the existing tests pass.
2023-02-13 14:05:16 +01:00
Jannis Harder
9f20beb7df
xprop: Smaller subset of tests to run by default
2023-02-13 14:02:02 +01:00
Jannis Harder
160eeab2bb
verilog_backend: Do not run bwmuxmap even if in expr mode
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While bwmuxmap generates equivalent logic, it doesn't propagate x bits
in the same way, which can be relevant when writing verilog.
2023-02-13 14:00:38 +01:00
Jannis Harder
1698202ccc
sim: For yw cosim, drive parent module's signals for input ports
2023-02-13 12:26:06 +01:00
github-actions[bot]
4c334b905f
Bump version
2023-02-13 00:17:46 +00:00
Dag Lem
615adc4253
Resolve package types in interfaces ( #3658 )
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* Resolve package types in interfaces
* Added test for resolving of package types in interfaces
2023-02-12 18:25:39 -05:00
Zachary Snow
26a6c60478
Add test for typenames using constants shadowed later on
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This possible edge case came up while reviewing #3555 . It is currently
handled correctly, but there is no clear test coverage.
2023-02-12 17:03:37 -05:00
github-actions[bot]
5ea2c290a5
Bump version
2023-02-11 00:14:42 +00:00
Jannis Harder
6d021f04d4
tests: Fix path of yosys invocation in xprop tests
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For now xprop test failures are still expected and ignored, but without
this change, they did not even run unless the yosys build was in path.
2023-02-10 19:17:16 +01:00
Jannis Harder
f3c4e93d24
Merge pull request #3667 from jix/xprop-test-make-fix
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tests: in xprop tests, use MAKE variable if set
2023-02-10 16:06:16 +01:00
Jannis Harder
d31d5da69f
tests: in xprop tests, use MAKE variable if set
2023-02-10 15:01:04 +01:00
github-actions[bot]
b1a011138c
Bump version
2023-02-09 01:17:36 +00:00
Miodrag Milanovic
a7099b0a72
Next dev cycle
2023-02-08 12:34:19 +01:00
Miodrag Milanovic
7e588664e7
Release version 0.26
2023-02-08 12:32:43 +01:00
Jannis Harder
ddb2bd85c8
Merge pull request #3662 from YosysHQ/micko/wide_case_select_box
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Add Verific import support for OPER_WIDE_CASE_SELECT_BOX
2023-02-08 12:22:30 +01:00
Miodrag Milanovic
5f33c0e0b2
Updated changelog
2023-02-08 10:11:47 +01:00
Miodrag Milanovic
109b88c379
For case select values use Sa instead of Sx and Sz
2023-02-08 09:22:48 +01:00
uis
ea6f562d49
gowin: Add new types of oscillator
2023-02-06 21:34:32 +00:00
N. Engelhardt
417fadbefd
Merge pull request #3625 from povik/show_cleanup
2023-02-06 16:11:26 +01:00
Miodrag Milanovic
e7e37df91b
Add verific import support for OPER_WIDE_CASE_SELECT_BOX
2023-02-06 09:28:23 +01:00
Dag Lem
777c589e85
Handle range offsets in packed arrays within packed structs
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This brings the metadata for packed arrays in packed structs
in line with the metadata for unpacked arrays, and correctly
handles the case when both lsb and msb in an address range are
non-zero.
2023-02-05 17:09:51 +01:00
github-actions[bot]
45edc8eb98
Bump version
2023-02-05 00:18:39 +00:00
Catherine
5fa96ccdee
Merge pull request #3659 from whitequark/update-abc
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Bump ABCREV to fix WASM build
2023-02-04 04:09:55 +00:00
Catherine
3af3cc15b5
Bump ABCREV to fix WASM build.
2023-02-04 03:35:53 +00:00
github-actions[bot]
54bf15a5b8
Bump version
2023-02-04 00:16:33 +00:00
Aki Van Ness
a90f940615
backends/firrtl: Ensure `modInstance` is valid
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This should fix #3648 where when calling `emit_elaborated_extmodules` it
checks to see if a module is a black-box, however there was no
validation that the cell type was actually known, and it just always
assumed that we would get a valid instance, causing a segfault.
2023-02-03 08:27:52 -05:00
github-actions[bot]
221036c5b6
Bump version
2023-02-02 00:17:21 +00:00
Jannis Harder
0f2cb80a26
Merge pull request #3655 from jix/smt2_fix_b_op_width
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smt2: Fix operation width computation for boolean producing cells
2023-02-01 18:06:59 +01:00
Jannis Harder
5e82638408
smt2: Fix operation width computation for boolean producing cells
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The output width for the boolean value should not influence the
operation width. The previous incorrect width extension would still
produce correct results, but could produce invalid smt2 output for
reduction operators when the output width was larger than the width of
the vector to which the reduction was applied.
This fixes #3654
2023-02-01 12:34:35 +01:00