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Merge pull request #3662 from YosysHQ/micko/wide_case_select_box 

Add Verific import support for OPER_WIDE_CASE_SELECT_BOX
This commit is contained in:
Jannis Harder 2023-02-08 12:22:30 +01:00 committed by GitHub
parent 5f33c0e0b2 109b88c379
commit ddb2bd85c8
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 82 additions and 4 deletions
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85
frontends/verific/verific.cc
View File

@ -361,10 +361,16 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn
for (unsigned i = 0; i < portbus->Size(); i++) {
Net *net = inst->GetNet(portbus->ElementAtIndex(i));
if (net) {
if (net->IsGnd())
sig.append(RTLIL::State::S0);
else if (net->IsPwr())
sig.append(RTLIL::State::S1);
if (net->IsConstant()) {
if (net->IsGnd())
sig.append(RTLIL::State::S0);
else if (net->IsPwr())
sig.append(RTLIL::State::S1);
else if (net->IsX())
sig.append(RTLIL::State::Sx);
else
sig.append(RTLIL::State::Sz);
}
else
sig.append(net_map_at(net));
} else
@ -379,6 +385,36 @@ RTLIL::SigSpec VerificImporter::operatorInport(Instance *inst, const char *portn
}
}
RTLIL::SigSpec VerificImporter::operatorInportCase(Instance *inst, const char *portname)
{
PortBus *portbus = inst->View()->GetPortBus(portname);
if (portbus) {
RTLIL::SigSpec sig;
for (unsigned i = 0; i < portbus->Size(); i++) {
Net *net = inst->GetNet(portbus->ElementAtIndex(i));
if (net) {
if (net->IsConstant()) {
if (net->IsGnd())
sig.append(RTLIL::State::S0);
else if (net->IsPwr())
sig.append(RTLIL::State::S1);
else
sig.append(RTLIL::State::Sa);
}
else
sig.append(net_map_at(net));
} else
sig.append(RTLIL::State::Sa);
}
return sig;
} else {
Port *port = inst->View()->GetPort(portname);
log_assert(port != NULL);
Net *net = inst->GetNet(port);
return net_map_at(net);
}
}
RTLIL::SigSpec VerificImporter::operatorOutput(Instance *inst, const pool<Net*, hash_ptr_ops> *any_all_nets)
{
RTLIL::SigSpec sig;
@ -989,6 +1025,47 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
return true;
}
if (inst->Type() == OPER_WIDE_CASE_SELECT_BOX)
{
RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value");
RTLIL::SigSpec sig_select = operatorInport(inst, "select");
RTLIL::SigSpec sig_select_values = operatorInportCase(inst, "select_values");
RTLIL::SigSpec sig_data_values = operatorInport(inst, "data_values");
RTLIL::SigSpec sig_data_default = operatorInport(inst, "default_value");
RTLIL::Process *proc = module->addProcess(new_verific_id(inst));
import_attributes(proc->attributes, inst);
RTLIL::CaseRule *current_case = &proc->root_case;
current_case = &proc->root_case;
RTLIL::SwitchRule *sw = new RTLIL::SwitchRule;
sw->signal = sig_select;
current_case->switches.push_back(sw);
int select_width = inst->InputSize();
int data_width = inst->OutputSize();
int select_num = inst->Input1Size() / inst->InputSize();
int offset_select = 0;
int offset_data = 0;
for (int i = 0; i < select_num; i++) {
RTLIL::CaseRule *cs = new RTLIL::CaseRule;
cs->compare.push_back(sig_select_values.extract(offset_select, select_width));
cs->actions.push_back(SigSig(sig_out_val, sig_data_values.extract(offset_data, data_width)));
sw->cases.push_back(cs);
offset_select += select_width;
offset_data += data_width;
}
RTLIL::CaseRule *cs_default = new RTLIL::CaseRule;
cs_default->actions.push_back(SigSig(sig_out_val, sig_data_default));
sw->cases.push_back(cs_default);
return true;
}
#undef IN
#undef IN1
#undef IN2

1
frontends/verific/verific.h
View File

@ -87,6 +87,7 @@ struct VerificImporter
RTLIL::SigSpec operatorInput1(Verific::Instance *inst);
RTLIL::SigSpec operatorInput2(Verific::Instance *inst);
RTLIL::SigSpec operatorInport(Verific::Instance *inst, const char *portname);
RTLIL::SigSpec operatorInportCase(Verific::Instance *inst, const char *portname);
RTLIL::SigSpec operatorOutput(Verific::Instance *inst, const pool<Verific::Net*, hash_ptr_ops> *any_all_nets = nullptr);
bool import_netlist_instance_gates(Verific::Instance *inst, RTLIL::IdString inst_name);