6 Commits

Author	SHA1	Message	Date
Clifford Wolf	9ac560f5d3	Add "dffinit -highlow" and fix synth_intel ... Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-01-09 18:42:19 +01:00
dh73	3fd1d61e2a	Initial Cyclone 10 support	2017-11-08 22:45:21 -06:00
Larry Doolittle	50bcd9a728	Clean whitespace and permissions in techlibs/intel	2017-10-05 16:23:49 +02:00
Clifford Wolf	65f91e5120	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	2017-10-03 17:31:21 +02:00
dh73	4718e65763	Tested and working altsyncarm without init files	2017-10-01 19:59:45 -05:00
dh73	cbaba62401	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now	2017-10-01 11:04:17 -05:00