riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
6,391 Commits 114 Branches 50 Tags 34 MiB
Commit Graph

12 Commits

Author SHA1 Message Date
Eddie Hung 675c1d4218 Add ice40_wrapcarry pass, rename $__ICE40_FULL_ADDER -> CARRY_WRAPPER 2019-08-07 16:29:38 -07:00
Eddie Hung 6b314c8371 Wrap SB_CARRY+SB_LUT into $__ICE40_FULL_ADDER 2019-08-07 16:29:38 -07:00
Eddie Hung 5fb27c071b $__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark 2019-07-15 12:03:51 -07:00
Eddie Hung c6e16e1334 _ABC macro will map and unmap to this new box 2019-07-12 00:51:37 -07:00
Eddie Hung 4da25c76b3 Ooopsie 2019-06-03 09:33:42 -07:00
Eddie Hung 437fec0d88 Map to SB_LUT4 from fastest input first 2019-04-17 13:01:17 -07:00
Eddie Hung c1ebe51a75 Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" 
This reverts commit a7632ab332.
 2019-04-17 11:10:20 -07:00
Eddie Hung a7632ab332 Try using an ICE40_CARRY_LUT primitive to avoid ABC issues 2019-04-17 11:10:04 -07:00
Tim 'mithro' Ansell d6bdefd2e9 Improving vpr output support. 
* Support output BLIF for Xilinx architectures.
 * Support using .names in BLIF for Xilinx architectures.
 * Use the same `NO_LUT` define in both `synth_ice40` and
  `synth_xilinx`.
 2018-04-18 16:55:12 -07:00
Clifford Wolf 234726c655 Add "synth_ice40 -vpr" 2017-11-16 21:37:02 +01:00
Clifford Wolf 0d344a23d3 improved ice40 dff cell mapping 2015-04-16 11:30:56 +02:00
Clifford Wolf 42d5d94a5d Added very first version of "synth_ice40" 2015-03-05 20:37:55 +01:00