Emily Schmidt
850b3a6c29
convert class FunctionalIR to a namespace Functional, rename functionalir.h to functional.h, rename functional.h to compute_graph.h
2024-08-21 11:04:08 +01:00
Emily Schmidt
00a65754bb
factor out SExpr/SExprWriter classes out of smtlib backend, and also tidy them up/document them
2024-08-21 11:03:27 +01:00
Miodrag Milanovic
e296b884d5
Add Makefile helpers for coverage
2024-08-21 11:02:31 +01:00
Emily Schmidt
6f9e21219b
add new generic compute graph and rewrite c++ functional backend to use it
2024-08-21 11:02:29 +01:00
Jannis Harder
56572978f5
drivertools: Utility code for indexing and traversing signal drivers
...
It adds `DriveBit`, `DriveChunk` and `DriveSpec` types which are similar
to `SigBit`, `SigChunk` and `SigSpec` but can also directly represent
cell ports, undriven bits and multiple drivers. For indexing an RTLIL
module and for querying signal drivers it comes with a `DriverMap` type
which is somewhat similar to a `SigMap` but is guaranteed to produce
signal drivers as returned representatives.
A `DriverMap` can also optionally preserve connections via intermediate
wires (e.g. querying the driver of a cell input port will return a
connected intermediate wire, querying the driver of that wire will
return the cell output port that's driving the wire).
2024-08-21 11:00:21 +01:00
github-actions[bot]
4cddc19994
Bump version
2024-08-20 00:18:24 +00:00
N. Engelhardt
7f08a298a4
Merge pull request #4542 from YosysHQ/krys/rtd
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Local readthedocs
2024-08-19 10:04:38 +02:00
github-actions[bot]
5fb3c0b1d9
Bump version
2024-08-17 00:17:44 +00:00
KrystalDelusion
3dd32d741a
Stop unconditionally building abc
...
_What are the reasons/motivation for this change?_
abc builds unconditional because `check-git-abc` is a phony prerequisite and therefore always runs, and since it always runs it will always trigger abc to rebuild.
_Explain how this is achieved._
Convert `check-git-abc` to an order-only prerequisite. It still runs as before, but no longer triggers yosys-abc to rebuild when it does.
_If applicable, please suggest to reviewers how they can test the change._
2024-08-17 11:04:17 +12:00
Krystine Sherwin
3b63ab07ae
docs: Build RTD artifacts directly
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Use rtds-action instead of yosys-cmd-ref repo.
Add rtds_action to docs configuration.
Add `.readthedocs.yaml`.
Update `DOCS_USAGE_` make target to be able to use pre-generated executables without forcing a remake.
2024-08-16 10:43:51 +12:00
github-actions[bot]
1eaf4e0790
Bump version
2024-08-15 00:17:57 +00:00
github-actions[bot]
4b9f452735
Bump version
2024-08-13 00:19:11 +00:00
github-actions[bot]
77b2ae2e39
Bump version
2024-08-08 00:18:08 +00:00
github-actions[bot]
669f8b18f0
Bump version
2024-08-07 00:18:20 +00:00
Miodrag Milanovic
d08bf671b2
Next dev cycle
2024-08-06 09:48:35 +02:00
Miodrag Milanovic
80ba43d262
Release version 0.44
2024-08-06 09:42:28 +02:00
Miodrag Milanović
e5d8505349
Merge pull request #4523 from YosysHQ/emil/no-lto-lld
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Makefile: no LTO and lld by default
2024-08-06 09:08:09 +02:00
github-actions[bot]
d2b5788674
Bump version
2024-08-06 00:18:14 +00:00
Emil J. Tywoniak
eeecb54532
Makefile: no LTO and lld by default
2024-08-05 19:28:09 +02:00
github-actions[bot]
c788484679
Bump version
2024-07-30 00:18:19 +00:00
Emil J
92cac63845
Merge pull request #4344 from widlarizer/emil/keep_hierarchy
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cost: add keep_hierarchy pass with min_cost argument
2024-07-29 16:33:08 +02:00
N. Engelhardt
9f869b265c
Merge pull request #4474 from tony-min-1/mchp
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Add PolarFire FPGA support
2024-07-29 15:28:44 +02:00
Emil J
e21dd292fc
Merge pull request #4502 from YosysHQ/emil/build-opt-levels
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Release build configuration improvements
2024-07-29 15:13:52 +02:00
Emil J. Tywoniak
4b29f64142
cost: add model for techmapped cell count, keep_hierarchy pass with -min_cost parameter
2024-07-29 10:26:02 +02:00
github-actions[bot]
960bca0196
Bump version
2024-07-27 00:17:35 +00:00
github-actions[bot]
610d27dc1c
Bump version
2024-07-26 00:17:42 +00:00
Emil J. Tywoniak
7cd27e1182
Makefile: remove accidental abc opt level override for wasi builds
2024-07-24 21:31:35 +02:00
Emil J. Tywoniak
bf758b9097
Makefile: turn off LTO on gcc due to regression
2024-07-22 20:59:56 +02:00
github-actions[bot]
28ebefda4a
Bump version
2024-07-19 00:17:55 +00:00
Martin Povišer
81df8557d9
Merge pull request #4494 from povik/install-bitpattern-h
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Makefile: do install `bitpattern.h`
2024-07-18 15:50:58 +02:00
Emil J
1d7a47bb6b
Merge pull request #4487 from YosysHQ/emil/abc-reproducible-git-hash
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Reproducible git hash
2024-07-18 11:54:07 +02:00
Martin Povišer
ec32c9a056
Makefile: do install `bitpattern.h`
2024-07-17 18:26:12 +02:00
github-actions[bot]
49f547782c
Bump version
2024-07-16 00:18:08 +00:00
Alexander von Gluck
2f514487cb
haiku: Basic fixes to build under Haiku
2024-07-15 12:57:34 +02:00
Emil J. Tywoniak
0cd55e1d7c
Makefile: fix
2024-07-12 11:00:36 +02:00
Emil J. Tywoniak
9d15f1d6ac
Makefile: reproducible .gitcommit
2024-07-12 10:52:03 +02:00
github-actions[bot]
b08688f711
Bump version
2024-07-10 00:18:13 +00:00
Emil J. Tywoniak
725746baa6
Makefile: LTO for all, lld for clang
2024-07-09 11:25:16 +02:00
Miodrag Milanovic
b9181aaad2
Next dev cycle
2024-07-09 09:27:23 +02:00
Miodrag Milanovic
c6e5e0b26b
Release version 0.43
2024-07-09 09:11:59 +02:00
Emil J. Tywoniak
ad22430b96
Makefile: use -O3 instead of -Os
2024-07-08 19:19:10 +02:00
Emil J. Tywoniak
fee274c76a
Makefile: let clang use -Og in debug builds
2024-07-08 18:16:04 +02:00
chunlin min
9de5602574
ininclude microchip tests in makefile
2024-07-04 15:54:59 -04:00
github-actions[bot]
a739e21a5f
Bump version
2024-06-29 00:16:56 +00:00
github-actions[bot]
1288166f7a
Bump version
2024-06-25 00:17:11 +00:00
Miodrag Milanović
1e401c3e04
Merge pull request #4460 from YosysHQ/micko/c++17
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Make C++17 compiler required
2024-06-24 19:54:30 +02:00
Miodrag Milanovic
777624ccf5
Make yosys-config dependant of Makefile
2024-06-24 16:08:08 +02:00
github-actions[bot]
6c8ae44ae7
Bump version
2024-06-20 00:17:08 +00:00
github-actions[bot]
ede3750a6c
Bump version
2024-06-19 00:17:13 +00:00
Miodrag Milanovic
141a2e3638
Make C++17 compiler required
2024-06-17 16:55:36 +02:00