Clifford Wolf
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6c84341f22
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Fixed trailing whitespaces
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2015-07-02 11:14:30 +02:00 |
Clifford Wolf
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f9a307a50b
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namespace Yosys
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2014-09-27 16:17:53 +02:00 |
Clifford Wolf
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cdae8abe16
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Renamed port access function on RTLIL::Cell, added param access functions
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2014-07-31 16:38:54 +02:00 |
Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
Clifford Wolf
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946ddff9ce
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Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26 20:12:50 +02:00 |
Clifford Wolf
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97a59851a6
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Added RTLIL::Cell::has(portname)
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2014-07-26 16:11:28 +02:00 |
Clifford Wolf
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f8fdc47d33
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Manual fixes for new cell connections API
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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b7dda72302
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
Clifford Wolf
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295e352ba6
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Renamed "placeholder" to "blackbox"
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2013-11-22 15:01:12 +01:00 |
Clifford Wolf
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84ced2bb8e
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Fixed a bug in "add -global_input"
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2013-11-21 03:01:20 +01:00 |
Clifford Wolf
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2279b2a196
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Added "add" command (only wires for now)
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2013-11-20 19:37:40 +01:00 |