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5 Commits

Author SHA1 Message Date
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes. 
Fixes #2058.
 2020-05-19 01:42:40 +02:00
Clifford Wolf 151db528e4 Fix missing newline at end of file 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-22 18:09:37 +02:00
Miodrag Milanovic 5f561bdcb1 Proper arith for Anlogic and use standard pass 2019-08-12 20:21:36 +02:00
Miodrag Milanovic 837cb0a1b9 anlogic : Fix alu mapping 2019-08-03 14:47:33 +02:00
Miodrag Milanovic 83bce9f59c Initial support for Anlogic FPGA 2018-12-01 18:28:54 +01:00