11 Commits

Author	SHA1	Message	Date
Eddie Hung	713484fa66	Do not do call equiv_opt when no sim model exists	2019-12-31 18:40:30 -08:00
Eddie Hung	c082329af3	Call equiv_opt with -multiclock and -assert	2019-12-31 18:39:32 -08:00
Eddie Hung	c2c74f9bb0	Merge pull request #1599 from YosysHQ/eddie/retry_1588 ... Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"	2019-12-30 10:01:02 -08:00
Eddie Hung	011f749ecf	Update resource count	2019-12-28 02:15:11 -08:00
Eddie Hung	d45869855c	Add #1598 testcase	2019-12-27 16:44:57 -08:00
Eddie Hung	caab66111e	Rename memory tests to lutram, add more xilinx tests	2019-12-12 17:44:37 -08:00
Miodrag Milanovic	3e0ffe05a7	Fixed tests	2019-11-11 15:41:33 +01:00
Miodrag Milanovic	12383f37b2	Common memory test now shared	2019-10-18 12:33:35 +02:00
Miodrag Milanovic	5603595e5c	Share common tests	2019-10-18 12:19:59 +02:00
Miodrag Milanovic	56f9482675	Fix path to yosys	2019-10-18 11:12:03 +02:00
Miodrag Milanovic	c2ec7ca703	Moved all tests in arch sub directory	2019-10-18 11:06:12 +02:00