yosys

Author	SHA1	Message	Date
Clifford Wolf	a62c21c9c6	Removed RTLIL::SigSpec::expand() method	2014-07-23 19:34:51 +02:00
Clifford Wolf	4b4048bc5f	SigSpec refactoring: using the accessor functions everywhere	2014-07-22 20:39:37 +02:00
Clifford Wolf	a233762a81	SigSpec refactoring: renamed chunks and width to __chunks and __width	2014-07-22 20:39:37 +02:00
Clifford Wolf	1241a9fd50	Added "opt_const -fine" and "opt_reduce -fine"	2014-07-21 16:34:16 +02:00
Clifford Wolf	309ae98246	Apply opt_reduce WR_EN opts to the whole mux tree driving the WR_EN port	2014-07-18 10:28:45 +02:00
Clifford Wolf	1b00861d0a	Improved opt_reduce handling of mem wr_en mux bits	2014-07-17 12:12:04 +02:00
Clifford Wolf	d678b6533d	improved opt_reduce for $mem/$memwr WR_EN multiplexers	2014-07-16 14:08:51 +02:00
Clifford Wolf	68c059565a	Fixed bug in opt_reduce (see vloghammer issue_044)	2014-05-12 12:45:47 +02:00
Clifford Wolf	9b9c3327cc	Fixed undef handling in opt_reduce	2014-03-06 14:18:34 +01:00
Clifford Wolf	e5b974fa2a	Cleanups and bugfixes in response to new internal cell checker	2013-11-11 00:39:45 +01:00
Clifford Wolf	36954471a6	Added help messages for opt_* passes	2013-03-01 09:01:49 +01:00
Clifford Wolf	a321a5c412	Moved stand-alone libs to libs/ directory and added libs/subcircuit	2013-02-27 09:32:19 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00