Clifford Wolf
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f71e27dbf1
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Remove auto_wire framework (smarter than the verilog standard)
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2013-11-24 17:29:11 +01:00 |
Clifford Wolf
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09471846c5
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Major improvements in mem2reg and added "init" sync rules
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2013-11-21 13:49:00 +01:00 |
Clifford Wolf
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1dcb683fcb
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Write yosys version to output files
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2013-11-03 21:41:39 +01:00 |
Clifford Wolf
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73914d1a41
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Added -selected option to various backends
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2013-09-03 19:10:11 +02:00 |
Clifford Wolf
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af79b4bd98
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Fixed generation of newlines in "dump" output
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2013-06-10 12:38:02 +02:00 |
Clifford Wolf
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21d9251e52
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Added "dump" command (part ilang backend)
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2013-06-02 17:53:30 +02:00 |
Clifford Wolf
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7fccad92f7
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Added more help messages
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2013-03-01 00:36:19 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |