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13793 Commits

Author SHA1 Message Date
Krystine Sherwin fae35fe98b
Docs: example_synth fifo update 
More detail on `memory_libmap`, the `$__ICE40_RAM4K_` intermediate step, and the
bizarre opt output.
 2024-01-30 13:34:29 +13:00
Krystine Sherwin fd0c574942
Docs: changes/todos from JF 2024-01-30 13:33:07 +13:00
Krystine Sherwin 9878e69d6c
Docs: tidying 
- Use `:file:` role for file names, as well as `:makevar:` and `:program:`.
- Remove deprecated `linux-arm` and `linux-riscv64` oss-cad-suite targets.
- Add link to ABC.
- More (and better) links to code examples.  Formatted `:file:` text with link
  to source on github.
- Includes a few extra todos (mostly picking up inline code blocks and a couple
  intro reminders).
- Fixing a few missing `:yoscrypt:` and `:cmd:ref:` tags.
- Reflowing some paragraphs for spacing/width.
 2024-01-30 13:31:00 +13:00
github-actions[bot] 112bcb0907 Bump version 2024-01-30 00:15:11 +00:00
N. Engelhardt 027cb31e9d
Merge pull request #4161 from YosysHQ/nak/add_sig_extract_asserts 
SigSpec/SigChunk::extract(): assert offset/length are not out of range
 2024-01-29 16:11:01 +01:00
Martin Povišer 2f4dd9961c
Merge pull request #4162 from jix/sim-print-sampling 
sim: Bring $print trigger/sampling semantics in line with FFs
 2024-01-29 15:39:46 +01:00
N. Engelhardt a9fe85c2d0
Merge pull request #4141 from YosysHQ/small_build 
Make small build links, and support Verific small build
 2024-01-29 15:17:39 +01:00
Jannis Harder fd838a99ce
Merge pull request #4140 from jix/writer_aiger_sccs 
write_aiger: Detect and error out on combinational loops
 2024-01-29 15:14:54 +01:00
N. Engelhardt 2282351172
Merge pull request #4118 from povik/fix-conn-on-wire-delete 
rtlil: Fix handling of connections on wire deletion
 2024-01-29 15:08:48 +01:00
Martin Povišer 23c9828d70 opt_clean: Remove dead branch 2024-01-29 11:26:44 +01:00
Martin Povišer 7afc0696e2 opt_clean: Assert an impossible path isn't taken 2024-01-29 11:26:44 +01:00
Martin Povišer ec065186d3 opt_clean: Add commentary around wire cleaning, NFC 2024-01-29 11:26:44 +01:00
Martin Povišer ea3dc7c1b4 rtlil: Add wire deletion test 2024-01-29 11:25:54 +01:00
Martin Povišer c035289383 rtlil: Do not create dummy wires when deleting wires in connections 2024-01-29 11:25:54 +01:00
Martin Povišer d6600fb1d5 rtlil: Fix handling of connections on wire deletion 2024-01-29 11:25:54 +01:00
github-actions[bot] 4585d60b8a Bump version 2024-01-28 00:17:09 +00:00
Miodrag Milanović 887c90500a
Merge pull request #4166 from YosysHQ/update-workflows 
Update workflows to Node.js 20
 2024-01-27 09:06:23 +01:00
Miodrag Milanović 54c5431cfc
Merge pull request #4167 from yrabbit/wip-byte-enable 
gowin: Change BYTE ENABLE handling.
 2024-01-27 09:04:42 +01:00
YRabbit a5fdf3f881 gowin: Change BYTE ENABLE handling. 
When inferring we allow writing to all bytes for now.

Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
 2024-01-27 17:19:49 +10:00
Krystine Sherwin a7e1c6e530
codeowners: adopting docs folder 2024-01-27 11:32:08 +13:00
Krystine Sherwin 7e524e0588
Update workflows to Node.js 20 
Node.js 16 actions are deprecated.  For more information see: https://github.blog/changelog/2023-09-22-github-actions-transitioning-from-node-16-to-node-20/.
 2024-01-27 11:20:48 +13:00
Philippe Sauter 68a9aa7c29 peepopt: handle offset too large in `shiftadd` 
If the offset is larger than the signal itself,
meaning the signal is completely shifted out,
it tried to extract a negative amount of bits from the old signal.

This RTL pattern is suspicious since it is a complicated way of
arriving at a constant value, so we warn the user.
 2024-01-26 16:44:30 +01:00
Krystine Sherwin 22808e0e3f
Docs: work on selections.rst 
Highlighting the difference between `select prod %ci` and `select prod %ci2` by
introducing `sumproud.out` using the `dump` command.

Playing around with advanced cone example code.
 2024-01-26 17:29:59 +13:00
Krystine Sherwin e2e7065590
Docs: some restructure of advanced section 
- Filling out index descriptions for `using_yosys` and `using_yosys/synthesis`.
- To discourage skipping over these index pages, the toctree in
  `using_yosys/index` is hidden and instead has inline links to the two
  subsections.
- Tidying todos.
- Moves technology mapping to `techmap_synth`, leaving the techmap by example in
  the internals section. `yosys_flows` gets split up, with the coarse-grain
  intro replaced by `synthesis/index`, the extract pass moving to
  `synthesis/extract` and model checking to `more_scripting/model_checking`.
 2024-01-26 13:08:22 +13:00
Krystine Sherwin 4582ab59da
Docs: intro to memory_libmap 2024-01-26 11:15:01 +13:00
Ethan Mahintorabi 33fe2e4613
fixes char* to string conversion issue 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-01-25 17:39:18 +00:00
Ethan Mahintorabi d2a04cca0e
write_verilog: Making sure BUF cells are converted to expressions. 
These were previously not being converted correctly leading to yosys
internal cells being written to my netlist.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-01-25 17:00:05 +00:00
Jannis Harder 7c818d30f7 sim: Bring $print trigger/sampling semantics in line with FFs 2024-01-25 16:21:03 +01:00
N. Engelhardt efe4d6dbdc SigSpec/SigChunk::extract(): assert offset/length are not out of range 2024-01-25 12:28:17 +01:00
github-actions[bot] 80511ced71 Bump version 2024-01-25 00:16:42 +00:00
Krystine Sherwin 6e38848b92
Docs: updating makefiles 2024-01-25 12:35:03 +13:00
Krystine Sherwin 62d2f89c74
Revert artifact reuse 2024-01-25 12:18:06 +13:00
Krystine Sherwin 2a14c72110
test-docs: target examples directly 2024-01-25 11:36:59 +13:00
Krystine Sherwin 4ac983e56c
test-docs: Checkout Yosys 2024-01-25 11:32:39 +13:00
Krystine Sherwin bb4d69005f
Docs: can we re-use build artifacts? 2024-01-25 10:15:43 +13:00
Krystine Sherwin 57a7532227
Docs: add test-examples target 
`test` becomes `test-macros`, with a new `test` calling both `test-*` targets.
 2024-01-25 10:15:00 +13:00
Krystine Sherwin e10d9b1fe0
Remove python dep from test-docs 2024-01-25 09:38:50 +13:00
Martin Povišer 6707db93b9
Merge pull request #4157 from whitequark/cxxrtl-fix-4144 
cxxrtl: fix typo in codegen for async set/clear
 2024-01-24 18:48:45 +01:00
Martin Povišer 08fd47e970 Test roundtripping some processes to Verilog and back 2024-01-24 16:32:25 +00:00
Catherine 9cbfad2691 write_verilog: don't emit code with dangling else related to wrong condition. 2024-01-24 16:32:25 +00:00
Catherine b841d1bcbe cxxrtl: fix typo in codegen for async set/clear. 2024-01-24 16:30:01 +00:00
github-actions[bot] 3c3788ee28 Bump version 2024-01-24 00:16:36 +00:00
Krystine Sherwin 9b820108d6
Docs: add test-docs.yml 2024-01-24 11:22:38 +13:00
Krystine Sherwin 449135a9d4
Docs: adding other macro command lists 
Also updates `macro_commands.py` to skip empty lines, and moves comment
stripping earlier in parsing.
 2024-01-24 10:29:40 +13:00
Krystine Sherwin 6c8949cacc
Docs: static opt macro list 
Also adds `docs/tests/macro_commands.py` which checks all commands in
`code_examples/macro_commands` against the current yosys build. Format similar
to `run-test.sh` files: logging the file under test and reporting errors.
 2024-01-24 09:56:00 +13:00
Gabriel Gouvine c634d59c18 Issue a warning instead of a syntax error for blif delay constraints 2024-01-23 16:25:16 +00:00
Miodrag Milanovic ddfd867d29 hardcode iverilog version so it works on forkes and in PRs 2024-01-23 17:22:56 +01:00
Krystine Sherwin 95849edbba
Docs: changes from JF 
`yosys-witness` prereq `click`.
Yosys environment vars & `yosys --help` output.
Removing Ubuntu/macOS version numbers/names.
Hide `troubleshooting` page.
 2024-01-23 17:35:06 +13:00
Krystine Sherwin e63f1f5367
Docs: merge CI fix 2024-01-23 16:39:04 +13:00
github-actions[bot] 2f9fcc2e50 Bump version 2024-01-23 00:16:43 +00:00