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yosys
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105 Commits

Author SHA1 Message Date
Clifford Wolf 161565be10 Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS) 2013-03-31 11:19:11 +02:00
Clifford Wolf 6a382f2aba Fixed handling of unconditional generate blocks 2013-03-26 09:44:54 +01:00
Clifford Wolf 227520f94d Added nosync attribute and some async reset related fixes 2013-03-25 17:13:14 +01:00
Clifford Wolf a321a5c412 Moved stand-alone libs to libs/ directory and added libs/subcircuit 2013-02-27 09:32:19 +01:00
Clifford Wolf 7764d0ba1d initial import 2013-01-05 11:13:26 +01:00