yosys

Author	SHA1	Message	Date
Claire Wolf	1f4e452609	Run bison with -Wall for verilog front-end Signed-off-by: Claire Wolf <claire@symbioticeda.com>	2020-07-15 11:49:36 +02:00
whitequark	dc35ef05f9	verilog_parser: turn S/R and R/R conflicts into hard errors. Fixes #2253.	2020-07-09 19:36:59 +00:00
Miodrag Milanovic	dc75ed7dac	Add one mode dependency	2020-03-19 16:53:40 +01:00
Kaj Tuomi	48ddbe52fb	Read bigger Verilog files. Hit parser limit with 3M gate design. This commit fix it.	2019-05-18 14:20:30 +03:00
Clifford Wolf	584d2030bf	Build Verilog parser with -DYYMAXDEPTH=100000, fixes #906 Signed-off-by: Clifford Wolf <clifford@clifford.at>	2019-03-29 16:32:44 +01:00
Clifford Wolf	ddc1761f1a	Add "make coverage" Signed-off-by: Clifford Wolf <clifford@clifford.at>	2018-08-27 14:22:21 +02:00
Clifford Wolf	e4ef000b70	Adjust makefiles to work with out-of-tree builds This is based on work done by Larry Doolittle	2015-08-12 15:04:44 +02:00
Fabio Utzig	fff6f00b3c	Enable bison to be customized	2015-01-08 09:56:20 -02:00
William Speirs	fad0b0c506	Updated lexers & parsers to include prefixes	2014-10-15 00:48:19 +02:00
Clifford Wolf	b17d6531c8	Added "make PRETTY=1"	2014-07-24 17:15:01 +02:00
Clifford Wolf	4a4a3fc337	Various improvements in support for generate statements	2013-12-04 21:06:54 +01:00
Clifford Wolf	7764d0ba1d	initial import	2013-01-05 11:13:26 +01:00