Clifford Wolf
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10e5791c5e
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Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-27 11:18:30 +02:00 |
Clifford Wolf
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4c4b602156
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Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-27 01:51:45 +02:00 |
Clifford Wolf
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f9946232ad
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Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-27 01:49:51 +02:00 |
Clifford Wolf
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b7dda72302
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Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
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2014-07-26 15:58:23 +02:00 |
Clifford Wolf
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cc4f10883b
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Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-26 11:58:03 +02:00 |
Clifford Wolf
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6aa792c864
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Replaced more old SigChunk programming patterns
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2014-07-24 23:10:58 +02:00 |
Clifford Wolf
|
c094c53de8
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Removed RTLIL::SigSpec::optimize()
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2014-07-23 20:32:28 +02:00 |
Clifford Wolf
|
4b4048bc5f
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SigSpec refactoring: using the accessor functions everywhere
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2014-07-22 20:39:37 +02:00 |
Clifford Wolf
|
a233762a81
|
SigSpec refactoring: renamed chunks and width to __chunks and __width
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2014-07-22 20:39:37 +02:00 |
Johann Glaser
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f13b3518aa
|
beautified write_intersynth
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2014-01-25 20:16:38 +01:00 |
Clifford Wolf
|
295e352ba6
|
Renamed "placeholder" to "blackbox"
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2013-11-22 15:01:12 +01:00 |
Clifford Wolf
|
4a60e5842d
|
Ignore explicit unconnected ports in intersynth backend
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2013-11-03 09:00:51 +01:00 |
Clifford Wolf
|
e9dede01ca
|
Fixed handling of boolean attributes (backends)
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2013-10-24 11:27:30 +02:00 |
Clifford Wolf
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73914d1a41
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Added -selected option to various backends
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2013-09-03 19:10:11 +02:00 |
Clifford Wolf
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05ae20f260
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Added -notypes option to intersynth backend
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2013-03-24 12:05:25 +01:00 |
Clifford Wolf
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a0fa259d81
|
Fixed gcc build (intersynth backend)
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2013-03-23 19:01:58 +01:00 |
Clifford Wolf
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bee57c808a
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Various improvements in intersynth backend
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2013-03-23 12:02:09 +01:00 |
Clifford Wolf
|
80aefb3eaa
|
Added intersynth backend
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2013-03-23 10:58:14 +01:00 |